DataSheet8.cn


PDF ( 数据手册 , 数据表 ) 68901P05

零件编号 68901P05
描述 MULTI.FUNCTION PERIPHERAL
制造商 STMicroelectronics
LOGO STMicroelectronics LOGO 


1 Page

No Preview Available !

68901P05 数据手册, 描述, 功能
MK68901
MULTI–FUNCTION PERIPHERAL
. 8 INPUT/OUTPUT PINS
Individually programmable direction
. Individual interrupt source capability
- Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
8 Internal sources
8 External sources
Individual source enable
Individual source masking
Programmable interrupt service modes
- Polling
- Vector generation
. - Optional In-service status
Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY PRO-
GRAMMABLE PRESCALING
Two multimode timers
- Delay mode
- Pulse width measurement mode
- Event counter mode
Two delay mode timers
. Independent clock input
Time out output option
SINGLE CHANNEL USART
Full Duplex
Asynchronous to 65 kbps
Byte synchronous to 1 Mbps
Internal/External baud rate generation
DMA handshake signals
.. Modem control
Loop back mode
68000 BUS COMPATIBLE
48 PIN DIP OR 52 PIN PLCC
1
DPIP48
Figure 1 : Pin connections.
PLCC52
DESCRIPTION
The MK68901 MFP (Multi-Function Peripheral) is a
combination of many of the necessary peripheral
functions in a microprocessor system.
Included are :
Eight parallel I/O lines
Interrrupt controller for 16 sources
Four timers
Single channel full duplex USART
The use of the MFP in a system can significantly re-
duce chip count, thereby reducing system cost. The
MFP is completely 68000 bus compatible, and 24 di-
rectly addressable internal registers provide the ne-
MFP
December 1988
1/33







68901P05 pdf, 数据表
MK68901
Figure 10 : A Conceptual Circuit of an Interrupt Channel.
V000356
There are two end-of-interrupt modes : the automat-
ic end-of-interrupt mode and the software end-of-in-
terrupt mode. The mode is selected by writing a one
or a zero to the S bit of the Vector Register (VR). If
the S bit of the VR is a one, all channels operate in
the software end-of-interrupt mode. If the S bit is a
zero, all channels operate in the automatic end-of-
interrupt mode, and a reset is held on all in-service
bits. In the automatic end-of-interrupt mode, the
pending bit is cleared when that channel passes its
vector. At that point, no further history of that inter-
rupt remains in the MK68901 MFP. In the software
end-of-interrupt mode, the in-service bit is set and
the pending bit is cleared when the channel passes
its vector. With the in-service bit set, no lower priority
channel is allowed to request an interrupt or to pass
its vector during an acknowledge sequence ; how-
ever, a lower priority channel may still receive an in-
terrupt and latch it into the pending bit. A higher prio-
rity channel may still request an interrupt and be ac-
knowledged. The in-service bit of a particular chan-
nel may be cleared by writing a zero to the corre-
sponding bit in ISRA or ISRB. Typically, this will be
done at the conclusion of the interrupt routine just
before the return. Thus no lower priority channel will
be allowed to request service until the higher priority
channel is complete, while channels of still higher
priority will be allowed to request service. While the
in-service bit is set, a second interrupt on that chan-
nel maybe received and latched into the pending bit,
though no service request will be made in re-
sponse to the second interrupt until the in-service bit
is cleared. ISRA and ISRB may be read at any time.
Only a zero may be written into any bit of ISRA and
ISRB ; thus the in-service bits may be cleared in soft-
ware but cannot be set in software. This allows any
one bit to be cleared, without altering any other bits,
simply by writing all ones except for the bit position
to be cleared to ISRA or ISRB, as with IPRA and
IPRB.
Figure 11 a : A Conceptual Circuit of the MK68901 MFP Daisy Chaining.
8/33
V000357







68901P05 equivalent, schematic
MK68901
There are two interrupt channels associated with the
receiver. One channel is used for the normal Buffer
Full condition, while the other channel is used whe-
never an error condition occurs. Only one interrupt
is generated per word received, but dedicating two
channels allows separate vectors : one for the nor-
mal condition, and one for an error condition. If the
error channel is disabled, an interrupt will be gen-e-
rated via the Butter Full Channel, whether the word
received is normal or in error. Those conditions
which produce an interrupt via the error channel
are : Overrun, Parity Error, Frame Error, Sync
Found, and Break. If a received word has an error
associated with it, and the error interrupt channel is
enabled, an interrupt will occur on the error channel
only.
Each time a word is transferred into the receive buf-
fer, a corresponding set of flags is latched into the
RSR. No flags (except CIP) are allowed to change
until the data word has been read from the receive
buffer. Reading the receive buffer allows a new data
word to be transferred to the receive buffer when it
is received. Thus one should first read the RSR then
read the receive buffer (UDR) to ensure that the
flags just read match the data word just read. If done
in the reverse order, it is possible that subsequent
to reading the data word from the receive buffer, but
prior to reading the RSR, a new word may be recei-
ved and transferred to the receive buffer and, with
it, its associated flags latched into the RSR. Thus,
when the RSR is read, those flags may actually cor-
respond to a different data word. It is good practice,
also to read the RSR prior to a data read as, when
an overrun error occurs, the receiver will not assem-
ble new characters until the RSR has been read.
As previously stated, when overrun occurs, the OE
flag will not be set and the associated interrupt will
not be generated until the receive buffer has been
read. If a break occurs, and the receive buffer has
not yet been read, only the B flag will be set (OE will
Figure 19 : Transmitter Status Register (TSR).
not be set). Again, this flag will not be set until the
last valid word has been read from the receive buf-
fer. If the break condition ends and another whole
data word is received before the receive buffer is
read, both the B and OE flags will be set once the
receive buffer is read.
If a break occurs while the OE flag is set, the B flag
will also be set.
A break generates an interrupt when the condition
occurs and again when the condition ends. If the
break condition ends before it is acknowledged by
reading the RSR, the receiver error interrupt indica-
ting end of break will be generated once the RSR is
read.
Anytime the asynchronous format is selected, start
bit detection is enabled. New data is not shifted into
the shift register until a zero bit is detected. If a ÷ 16
clock is selected, along with the asynchronous for-
mat, false start bit detection is also enabled. Any
transition has to be stable for 3 positive going edges
of the receive clock to be called a valid transition. For
a start bit to be good, a valid 0-1 transition must not
occur for 8 positive clock transitions after the initial
valid 1-0 transition.
After a good start bit has been detected, valid tran-
sitions in the data are checked for continously.
When a valid transition is detected, the counter is
forced to state zero, andno more transition checking
is started until state four. At state eight, the ”previous
state” of the transition checking logic is clocked into
the receiver.
As a result of this resynchronization logic, it is pos-
sible to run with asynchronous clocks without start
and stop bits if there are sufficient valid transitions
in the data stream. This logic also makes the unit
more tolerant of clock skew for normal asynchro-
nous communications than a device which employs
only start bit synchronization.
16/33
V000365










页数 33 页
下载[ 68901P05.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
68901P04MULTI.FUNCTION PERIPHERALSTMicroelectronics
STMicroelectronics
68901P05MULTI.FUNCTION PERIPHERALSTMicroelectronics
STMicroelectronics

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap