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PDF ( 数据手册 , 数据表 ) 74ACQ646SC

零件编号 74ACQ646SC
描述 Quiet Series Octal Transceiver/Register with 3-STATE Outputs
制造商 Fairchild Semiconductor
LOGO Fairchild Semiconductor LOGO 


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74ACQ646SC 数据手册, 描述, 功能
January 1990
Revised September 2000
74ACQ646 74ACTQ646
Quiet SeriesOctal Transceiver/Register
with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental handling functions
available are illustrated in Figure 1, Figure 2, Figure 3 and
Figure 4.
The ACQ/ACTQ utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Independent registers for A and B busses
s Multiplexed real-time and stored data transfers
s 300 mil slim dual-in-line package
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT646
Ordering Code:
Order Number Package Number
Package Description
74ACQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0A7
B0B7
CPAB, CPBA
SAB, SBA
G
DIR
Descriptions
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS010635
www.fairchildsemi.com







74ACQ646SC pdf, 数据表
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, VIL,until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 5. Quiet Output Noise Voltage Waveforms
Note 20: VOHV and VOLP are measured with respect to ground reference.
Note 21: Input pulses have the following characteristics: f = 1 MHz,
tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 6. Simultaneous Switching Test Circuit
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