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PDF ( 数据手册 , 数据表 ) 74ALVCH162240

零件编号 74ALVCH162240
描述 Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold and 26 Series Resistors in Outputs
制造商 Fairchild Semiconductor
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74ALVCH162240 数据手册, 描述, 功能
November 2001
Revised November 2001
74ALVCH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold and 26Series Resistors in Outputs
General Description
The ALVCH162240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH162240 is also designed with 26series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162240 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74ALVCH162240 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminating the need for external
pull-up/pull-down resistors
s 26series resistors in outputs
s tPD
3.8 ns max for 3.0V to 3.6V VCC
4.3 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Descriptions
74ALVCH162240T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500700
www.fairchildsemi.com












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