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零件编号 | 74ALVC16836ADGG | ||
描述 | 20-bit registered driver with inverted register enable 3-State | ||
制造商 | NXP Semiconductors | ||
LOGO | |||
1 Page
INTEGRATED CIRCUITS
74ALVC16836A
20-bit registered driver with
inverted register enable (3-State)
Product specification
Replaces datasheet 74ALVC16836 of 2000 Jan 04
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Product specification
74ALVC16836A
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V AND
VCC = 2.7 V RANGE
VM = 1.5 VCC
VX = VOL + 0.3 V
VY = VOH – 0.3 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = 2.7 V
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE
VM = 0.5 V
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
VI
An
INPUT
VM
GND
VOH
tPHL
tPLH
Yn
OUTPUT
VM
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00132
Waveform 1. Input (An) to output (Yn) propagation delay
VI
LE INPUT
GND
VM
tW
tPHL
VM
tPLH
VOH
Yn OUTPUT
VM
VOL
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
SH00165
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
ÉÉÉVI
An
ÉÉÉINPUT
ÉÉÉGND
VM
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
th th
VI
LE
INPUT
tSU
VM
tSU
GND
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00166
Waveform 3. Data set-up and hold times for the An input to the
LE input
VI
CP INPUT
GND
1/fMAX
VM
tW
tPHL
VM
tPLH
VOH
Yn OUTPUT
VM
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00135
Waveform 4. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
VI
CP INPUT
VM
GND
An
VI
INPUT
GND
ÉÉÉÉÉÉÉÉÉÉÉÉtsu ÉÉÉth ÉÉÉÉÉÉÉÉÉÉÉÉtsuÉÉÉthÉÉÉÉÉÉ
VOH
Yn OUTPUT
VM
VOL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00136
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
VI
nOE INPUT
GND
VM
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
tPLZ
VX
tPZL
VM
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
tPHZ
VY
tPZH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00137
Waveform 6. 3-State enable and disable times
2000 Mar 14
8
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页数 | 12 页 | ||
下载 | [ 74ALVC16836ADGG.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
74ALVC16836ADGG | 20-bit registered driver with inverted register enable 3-State | NXP Semiconductors |
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