|
|
零件编号 | 74ACTQ374QSC | ||
描述 | Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs | ||
制造商 | Fairchild Semiconductor | ||
LOGO | |||
1 Page
April 2007
74ACQ374, 74ACTQ374
Quiet Series™ Octal D-Type Flip-Flop with 3-STATE
tm
Outputs
Features
■ ICC and IOZ reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Buffered positive edge-triggered clock
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24mA
■ Faster prop delays than the standard AC/ACT374
General Description
The ACQ/ACTQ374 is a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The ACQ/ACTQ374 utilizes FACT Quiet Series™ tech-
nology to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
www.DataSheet4U.com
Ordering Information
Package
Order Number Number
Package Description
74ACQ374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACQ374SJ
74ACTQ374SC
M20D
M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACTQ374SJ
74ACTQ374QSC
M20D
MQA20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
www.fairchildsemi.com
FACT Noise Characteristics
The setup of a noise characteristics measurement is
critical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to
measure the noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are at
the correct voltage.
4. Set the HFS generator to toggle all but one output at
a frequency of 1MHz. Greater frequencies will
increase DUT heating and effect the results of the
measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
■ Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50Ω coaxial cable plugged into a
standard SMB type connector on the test fixture. Do
not use an active FET probe.
■ Measure VOLP and VOLV on the quiet output during
the worst case transition for active and enable.
Measure VOHP and VOHV on the quiet output during
the worst case active and enable transition.
■ Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
VILD and VIHD:
■ Monitor one of the switching outputs using a 50Ω
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
■ First increase the input LOW voltage level, VIL, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input LOW voltage level at
which oscillation occurs is defined as VILD.
■ Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as VIHD.
■ Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Notes:
16. VOHV and VOLP are measured with respect to ground
reference.
17. Input pulses have the following characteristics:
f = 1MHz, tr = 3ns, tf = 3ns, skew < 150ps.
Figure 1. Quiet Output Noise Voltage Waveforms
Figure 2. Simultaneous Switching Test Circuit
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
8
www.fairchildsemi.com
|
|||
页数 | 12 页 | ||
下载 | [ 74ACTQ374QSC.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
74ACTQ374QSC | Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs | Fairchild Semiconductor |
零件编号 | 描述 | 制造商 |
STK15C88 | 256-Kbit (32 K x 8) PowerStore nvSRAM | Cypress Semiconductor |
NJM4556 | DUAL HIGH CURRENT OPERATIONAL AMPLIFIER | New Japan Radio |
EL1118-G | 5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLER | Everlight |
DataSheet8.cn | 2020 | 联系我们 | 搜索 | Simemap |