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PDF ( 数据手册 , 数据表 ) 5256VA

零件编号 5256VA
描述 In-System Programmable 3.3V SuperWIDE High Density PLD
制造商 Lattice Semiconductor
LOGO Lattice Semiconductor LOGO 


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5256VA 数据手册, 描述, 功能
ispLSI® 5256VA
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
• SuperWIDE HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 192 I/O Pins
— 256 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package
Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Boundary
Scan
Interface
Global Routing Pool
(GRP)
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
5256va_04
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5256VA pdf, 数据表
Specifications ispLSI 5256VA
Figure 6. Boundary Scan Register Circuit for I/O Pins
EXTEST
HIGHZ
SCANIN
(from previous
cell)
BSCAN
Registers
DQ
BSCAN
Latches
DQ
TOE
Normal
Function
OE
0
1
EXTEST
PROG_MODE
DQ
DQ
Normal
Function
0
1
I/O Pin
DQ
SCANOUT
(to next cell)
Shift DR
Clock DR
Update DR
Reset
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell)
Shift DR
Clock DR
DQ
SCANOUT
(to next cell)
8







5256VA equivalent, schematic
Specifications ispLSI 5256VA
Power Consumption
Power consumption in the ispLSI 5256VA device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of four product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of four. The fast high-speed
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower low-
powersetting will significantly reduce the power
dissipation for these product terms. Figure 10 shows the
relationship between power and operating speed.
Figure 10. Typical Device Power Consumption vs fmax
400 ispLSI 5256VA
High Speed Mode
350
300
250
200 ispLSI 5256VA
Low Power Mode
150
100
0
20 40 60 80 100 120
fmax (MHz)
Notes: Configuration of 16 16-bit Counters
Typical Current at 3.3V, 25° C
140
ICC can be estimated for the ispLSI 5256VA using the following equation:
High Speed Mode: ICC = 30 + (# of PTs * 0.456) + (# of nets * Max. freq * 0.0039)
Low Power Mode: ICC = 30 + (# of PTs * 0.22) + (# of nets * Max. freq * 0.0039)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of 2 GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127/5256va
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