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PDF ( 数据手册 , 数据表 ) 5962-9095501MRA

零件编号 5962-9095501MRA
描述 DC-Coupled Demodulating 120 MHz Logarithmic Amplifier
制造商 Analog Devices
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5962-9095501MRA 数据手册, 描述, 功能
a
DC-Coupled Demodulating
120 MHz Logarithmic Amplifier
AD640*
FEATURES
Complete, Fully Calibrated Monolithic System
Five Stages, Each Having 10 dB Gain, 350 MHz BW
Direct Coupled Fully Differential Signal Path
Logarithmic Slope, Intercept and AC Response are
Stable Over Full Military Temperature Range
Dual Polarity Current Outputs Scaled 1 mA/Decade
Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.)
Low Power Operation (Typically 220 mW at ؎5 V)
Low Cost Plastic Packages Also Available
APPLICATIONS
Radar, Sonar, Ultrasonic and Audio Systems
Precision Instrumentation from DC to 120 MHz
Power Measurement with Absolute Calibration
Wide Range High Accuracy Signal Compression
Alternative to Discrete and Hybrid IF Strips
Replaces Several Discrete Log Amp ICs
PRODUCT DESCRIPTION
The AD640 is a complete monolithic logarithmic amplifier. A single
AD640 provides up to 50 dB of dynamic range for frequencies
from dc to 120 MHz. Two AD640s in cascade can provide up to
95 dB of dynamic range at reduced bandwidth. The AD640 uses a
successive detection scheme to provide an output current propor-
tional to the logarithm of the input voltage. It is laser calibrated to
close tolerances and maintains high accuracy over the full military
temperature range using supply voltages from ±4.5 V to ± 7.5 V.
The AD640 comprises five cascaded dc-coupled amplifier/limiter
stages, each having a small signal voltage gain of 10 dB and a –3 dB
bandwidth of 350 MHz. Each stage has an associated full-wave
detector, whose output current depends on the absolute value of its
input voltage. The five outputs are summed to provide the video
output (when low-pass filtered) scaled at 1 mA per decade (50 µA
per dB). On chip resistors can be used to convert this output cur-
rent to a voltage with several convenient slope options. A balanced
signal output at +50 dB (referred to input) is provided to operate
AD640s in cascade.
The logarithmic response is absolutely calibrated to within ±1 dB
for dc or square wave inputs from ± 0.75 mV to ± 200 mV, with
an intercept (logarithmic offset) at 1 mV dc. An integral X10
attenuator provides an alternative input range of ± 7.5 mV to
± 2 V dc. Scaling is also guaranteed for sinusoidal inputs.
The AD640B is specified for the industrial temperature range of
–40°C to +85°C and the AD640T, available processed to MIL-
STD-883B, for the military range of –55°C to +125°C. Both are
available in 20-lead side-brazed ceramic DIPs or leadless chip
carriers (LCC). The AD640J is specified for the commercial
temperature range of 0°C to +70°C, and is available in both
20-lead plastic DIP (N) and PLCC (P) packages.
This device is now available to Standard Military Drawing
(DESC) number 5962-9095501MRA and 5962-9095501M2A.
PRODUCT HIGHLIGHTS
1. Absolute calibration of a wideband logarithmic amplifier is
unique. The AD640 is a high accuracy measurement device,
not simply a logarithmic building block.
2. Advanced design results in unprecedented stability over the
full military temperature range.
3. The fully differential signal path greatly reduces the risk of
instability due to inadequate power supply decoupling and
shared ground connections, a serious problem with com-
monly used unbalanced designs.
4. Differential interfaces also ensure that the appropriate ground
connection can be chosen for each signal port. They further
increase versatility and simplify applications. The signal input
impedance is ~500 kin shunt with ~2 pF.
5. The dc-coupled signal path eliminates the need for numerous
interstage coupling capacitors and simplifies logarithmic
conversion of subsonic signals.
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
COM 18
RG1 1kRG0 1kRG2
17 16 15
LOG OUT LOG COM
14 13
INTERCEPT POSITIONING BIAS
12 +VS
ATN OUT 19
SIG +IN 20
SIG –IN 1
ATN LO 2
ATN COM 3
ATN COM 4
27
30
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
270
5
ATN IN
6
BL1
*Protected under U.S. patent number 4,990,803.
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
10dB
10dB
10dB
10dB
AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER
GAIN BIAS REGULATOR
7 SLOPE BIAS REGULATOR
–VS
11 SIG +OUT
10 SIG –OUT
9 BL2
8 ITC
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999







5962-9095501MRA pdf, 数据表
AD640
50 µA/dB, or 1 mA per decade. This scaling parameter is
trimmed to absolute accuracy using a 2 kHz square wave. At
frequencies near the system bandwidth, the slope is reduced due
to the reduced output of the limiter stages, but it is still rela-
tively insensitive to temperature variations so that a simple ex-
ternal slope adjustment in restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the
pedestal current from the summed detector outputs. It is ad-
justed during manufacture such that the output (flowing into
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly
± 10 mV is applied to the AD640. This places the dc intercept at
precisely 1 mV. The LOG COM output (Pin 13) is the comple-
ment of LOG OUT. It also has a 1 mV intercept, but with an
inverted slope of –1 mA/decade. Because its pedestal is very
large (equivalent to about 100 dB), its intercept voltage is not
guaranteed. The intercept positioning currents include a special
internal temperature compensation (ITC) term which can be
disabled by connecting Pin 8 to ground.
The logarithmic function of the AD640 is absolutely calibrated
to within ± 0.3 dB (or ± 15 µA) for 2 kHz square-wave inputs of
± 1 mV to ± 100 mV, and to within ± 1 dB between ± 750 µV and
± 200 mV. Figure 18 is a typical plot of the dc transfer function,
showing the outputs at temperatures of –55°C, +25°C and
+125°C. While the slope and intercept are seen to be little af-
fected by temperature, there is a lateral shift in the endpoints of
the “linear” region of the transfer function, which reduces the
effective dynamic range. The cause of this shift is explained in
Fundamentals of Logarithmic Conversion section.
2.5
+125؇C
+25؇C 2
2.0
–55؇C
1
0
1.5
–55؇C
–1
+25؇C
–2
1.0 +125؇C
0.5
0
–0.5
0.1
1.0
10.0
100.0
INPUT VOLTAGE – mV
1000.0
Figure 18. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25 °C, Input Direct
to Pins 1 and 20
The on chip attenuator can be used to handle input levels 20 dB
higher, that is, from ± 7.5 mV to ± 2 V for dc or square wave
inputs. It is specially designed to have a positive temperature
coefficient and is trimmed to position the intercept at 10 mV dc
(or –24 dBm for a sinusoidal input) over the full temperature
range. When using the attenuator the internal bias compensa-
tion should be disabled by grounding Pin 8. Figure 19 shows
the output at –55°C, +25°C, +85°C and +125°C for a single
AD640 with the attenuator in use; the curves overlap almost
perfectly, and the lateral shift in the transfer function does not
occur. Therefore, the full dynamic range is available at all
temperatures.
The output of the final limiter is available in differential form at
Pins 10 and 11. The output impedance is 75 to ground from
either pin. For most input levels, this output will appear to have
2.5
+25؇C
–55؇C
2.0
+85؇C
+125؇C
1.5
1
0
–1
–2
1.0
0.5
0
–0.5
1
10 100 1000
INPUT VOLTAGE – mV
10000
Figure 19. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, +85 °C and
+125 °C, Input via On-Chip Attenuator
roughly a square waveform. The signal path may be extended
using these outputs (see OPERATION OF CASCADED
AD640s). The logarithmic outputs from two or more AD640s
can be directly summed with full accuracy.
A pair of 1 kapplications resistors, RG1 and RG2 (Figure 17)
are accessed via Pins 15, 16 and 17. These can be used to con-
vert an output current to a voltage, with a slope of 1 V/decade
(using one resistor), 2 V/decade (both resistors in series) or
0.5 V/decade (both in parallel). Using all the resistors from two
AD640s (for example, in a cascaded configuration) ten slope
options from 0.25 V to 4 V/decade are available.
FUNDAMENTALS OF LOGARITHMIC CONVERSION
The conversion of a signal to its equivalent logarithmic value
involves a nonlinear operation, the consequences of which can be
very confusing if not fully understood. It is important to realize
from the outset that many of the familiar concepts of linear
circuits are of little relevance in this context. For example, the
incremental gain of an ideal logarithmic converter approaches
infinity as the input approaches zero. Further, an offset at the
output of a linear amplifier is simply equivalent to an offset at
the input, while in a logarithmic converter it is equivalent to a
change of amplitude at the input—a very different relationship.
We assume a dc signal in the following discussion to simplify the
concepts; ac behavior and the effect of input waveform on cali-
bration are discussed later. A logarithmic converter having a
voltage input VIN and output VOUT must satisfy a transfer func-
tion of the form
VOUT = VY LOG (VIN/VX)
Equation (1)
where Vy and Vx are fixed voltages which determine the scaling
of the converter. The input is divided by a voltage because the
argument of a logarithm has to be a simple ratio. The logarithm
must be multiplied by a voltage to develop a voltage output.
These operations are not, of course, carried out by explicit com-
putational elements, but are inherent in the behavior of the
converter. For stable operation, VX and VY must be based on
sound design criteria and rendered stable over wide temperature
and supply voltage extremes. This aspect of RF logarithmic
amplifier design has traditionally received little attention.
When VIN = VX, the logarithm is zero. VX is, therefore, called
the Intercept Voltage, because a graph of VOUT versus LOG (VIN)
—ideally a straight line—crosses the horizontal axis at this point
–8– REV. C







5962-9095501MRA equivalent, schematic
AD640
be increased and U3 can be replaced by a low speed op amp.
Figure 31 shows typical performance of this converter.
10 Hz–100 kHz Converter with 95 dB Dynamic Range
To increase the dynamic range it is necessary to reduce the
bandwidth by the inclusion of a low-pass filter at the signal
interface between U1 and U2 (Figure 32). To provide operation
down to low frequencies, dc coupling is used at the interface
between AD640s and the input offset is nulled by a feedback
circuit.
Using values of 0.02 µF in the interstage filter formed by capaci-
tors C1 and C2, the hf corner occurs at about 100 kHz. U3
(AD712) forms a 4-pole 35 Hz low-pass filter. This provides
operation to signal frequencies below 20 Hz. The filter response
is not critical, allowing the use of an electrolytic capacitor to
form one of the poles.
R1 is restricted to 50 by the compliance at Pin 14, so C3
needs to be large to form a 5 ms time constant. A tantalum
capacitor is used (note polarity). The output of U3a is scaled
+1 V per decade, and the X2 gain of U3b raises this to +2 V per
decade, or +100 mV/dB. The differential offset at the output of
U2 is low-pass filtered by R6/C7 and R7/C8 and buffered by
voltage followers U4a and U4b. The 16s open loop time constant
translates to a closed loop high-pass corner of 10 Hz. (This
high-pass filter is only operative for very small inputs; see page
13.) Figure 33 shows the performance for square wave inputs.
Since the attenuator is used, the upper end of the dynamic
range now extends to +6 dBV and the intercept is at –82 dBV.
The noise limited dynamic range is over 100 dB, but in practice
spurious signals at the input will determine the achievable range.
92
80
7 –2
6
5
4
3
2
1
0
–1
–90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 dBV
31.61003161m 3.16m 10m 31.6m 100m 316m 1 3.16 V
INPUT AMPLITUDE AT 10kHz
Figure 33. Logarithmic Output and Nonlinearity for Circuit
of Figure 32, for a Square Wave Input at f = 10 kHz
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Ceramic DIP (D) Package
0.430 (10.16)
0.320 (8.13)
0.300 (7.62)
20
1
11
0.300 (7.62)
0.280 (7.11)
10
PIN 1
1.010 (25.65)
0.990 (25.15)
0.095
(2.41)
SEATING
PLANE
0.020 (0.51)
0.015 (0.38)
0.10
(2.54)
0.085
(2.16)
0.210 (5.33)
0.150 (3.81)
0.012 (0.30)
0.008 (0.20)
0.054 (1.37)
0.040 (1.01)
0.300 (7.62)
20-Lead Plastic DIP (N) Package
1.070 (27.18)
0.310
(7.874)
TYP
20
1
PIN 1
0.125 (3.18)
MIN
0.021 (0.533) 0.100
0.015 (0.381)
(2.54)
TYP
11 0.250
(6.350)
10 TYP
0.045 (1.143)
0.025 (0.635)
0.300 (7.62)
TYP
0.180
(4.572)
MAX
0.033
(0.838)
SEATING
PLANE
TYP
15؇
0؇
0.014 (0.356)
0.008 (0.203)
20-Terminal Ceramic LCC (E) Package
0.082 ؎ 0.018
(2.085 ؎ 0.455)
0.050
(1.27)
0.350
(8.89
؎
؎
0.008
0.20)
SQ
13
14
19
18
PIN 1
INDEX
20
1
0.040 ؋ 45؇
(1.02 ؋ 45؇)
REF 3 PLCS
0.025 ؎ 0.003
(0.635 ؎ 0.075)
8
9
4
3
BOTTOM VIEW
0.20 ؋ 45؇
(0.51 ؋ 45؇)
REF
20-Lead PLCC (P) Package
0.390
(9.905
؎
؎
0.005
0.125)
SQ
0.045 ؎ 0.003
(1.143 ؎ 0.076)
3 19
4
PIN 1
18
IDENTIFIER
0.020
(0.51)
MAX
TOP VIEW
(PINS DOWN)
8
9
14
13
0.020 (0.51)
MAX
0.353
(8.966
؎
؎
0.003
0.076)
SQ
0.173 ؎ 0.008
(4.385 ؎ 0.185)
0.050
(1.27)
0.105 ؎ 0.015
(2.665 ؎ 0.375)
0.020 (0.51) MIN
R
0.035 ؎ 0.01
(0.89 ؎ 0.25)
0.029 ؎ 0.003
(0.737 ؎ 0.076)
0.017 ؎ 0.004
(0.432 ؎ 0.101)
0.025 (0.64) MIN
0.060 (1.53) MIN
–16–
REV. C










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