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PDF ( 数据手册 , 数据表 ) 5962-9067802MXC

零件编号 5962-9067802MXC
描述 High Performance Microprocessor with Memory Management and Protection
制造商 Intersil Corporation
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5962-9067802MXC 数据手册, 描述, 功能
80C286/883
March 1997
High Performance Microprocessor with Memory
Management and Protection
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Compatible with NMOS 80286/883
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
• Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
• Compatible with 80287 Numeric Data Co-Processor
The Intersil 80C286/883 is a static CMOS version of the
NMOS 80286 microprocessor. The 80C286/883 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. The 80C286/883 has built-in memory protection that
supports operating system and task isolation as well as pro-
gram and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 224
bytes (16 megabytes) of physical memory.
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a super-
set of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code com-
patible with existing 80C86 and 80C88 software. In protected
virtual address mode, the 80C286/883 is source code com-
patible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883’s integrated memory management and protec-
tion mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
The 80C286/883 provides special operations to support the
efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present excep-
tion and restartable instructions.
Ordering Information
PACKAGE TEMP. RANGE
10MHz
12.5MHz
16MHz
68 Pin PGA 0oC to +70oC
-
CG80C286-12
CG80C286-16
-40oC to +85oC IG80C286-10
IG80C286-12
-
-55oC to +125oC MG80C286-10/883 MG80C286-12/883
-
5962-9067801MXC 5962-9067802MXC
-
20MHz
CG80C286-20
-
-
-
25MHz
-
-
-
-
PKG. NO.
G68.B
G68.B
G68.B
G68.B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-128
File Number 2948.1







5962-9067802MXC pdf, 数据表
80C286/883
Waveforms
BUS CYCLE TYPE
VOH
CLK
TI
3 φ2
2
VOL
12A
READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES
TS TC
1 φ2 φ1 φ2
12B
WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE
TS TC
φ1 φ2 φ1 φ2
TC
φ1 φ2
READ
(TI OR TS)
φ1
S1 • S0
A23 - A0
M/IO,
COD INTA
BHE, LOCK
D15 - D0
READY
SRDY +
SRDYEN
ARDY +
ARDYEN
PCLK
ALF
CMDLY
MWTC
19
13
19
13
VALID ADDRESS
13
VALID CONTROL
VALID ADDRESS
13
VALID CONTROL
9
14
8
VALID READ DATA
11
10
VALID WRITE DATA
11
10
VALID IF TS
15
12
11
19 14
13
19 19
20
16 17
12
13
13
12
13
12
29
30
MRDC
DT/R
29 30
19
(SEE NOTE 1)
DEN
20 21
22
23
NOTES:
1. The modified timing is due to the CMDLY signal being active.
2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.
FIGURE 2. MAJOR CYCLE TIMING
24
3-135














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