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PDF ( 数据手册 , 数据表 ) EA218EI6B

零件编号 EA218EI6B
描述 EA218E 8-Port Ethernet Access Controller XpressFlow 2020 Ethernet Routing Switch Chipset
制造商 Zarlink Semiconductor Inc
LOGO Zarlink Semiconductor Inc LOGO 


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EA218EI6B 数据手册, 描述, 功能
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EA218EI6B pdf, 数据表
PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
EA218E
8-Port 10Mb Ethernet Access Controller
1.3 Pin Reference Table: (352 pin BGA)
Pin #
Signal Name
F26 P_A[1]
G24 P_A[2]
E25 P_A[3]
E26 P_A[4]
F24 P_A[5]
D25 P_A[6]
D26 P_A[7]
E24 P_A[8]
C25 P_A[9]
D24 P_A[10]
C26 P_A[11]
F25 P_ADS#
G26 P_CS#
H25 P_RWC
G25 P_BS16#
J24 P_RDY#
J26 P_RST#
H26 P_INT
K24 P_CLK
P25 P_D[0]
P26 P_D[1]
R24 P_D[2]
N25 P_D[3]
N26 P_D[4]
P24 P_D[5]
M25 P_D[6]
N24 P_D[7]
M26 P_D[8]
L25 P_D[9]
M24 P_D[10]
L26 P_D[11]
K25 P_D[12]
L24 P_D[13]
K26 P_D[14]
J25 P_D[15]
D13 S_CLK
A13 S_OVLD#
B23 S_HPREQ#
A24 S_REQ#
B24 S_GNT#
B12 S_MSGEN#
A12 S_EOF#
C14 S_IRDY
C13 S_TABT#
B13 S_D[0]
C15 S_D[1]
A14 S_D[2]
D15 S_D[3]
B14 S_D[4]
C16 S_D[5]
A15 S_D[6]
B15 S_D[7]
A16 S_D[8]
C17 S_D[9]
B16 S_D[10]
D17 S_D[11]
A17 S_D[12]
Note:
Pin #
Signal Name
Pin #
Signal Name
C18 S_D[13]
B17 S_D[14]
A18 S_D[15]
B18 S_D[16]
C19 S_D[17]
A19 S_D[18]
B19 S_D[19]
C20 S_D[20]
A20 S_D[21]
B20 S_D[22]
A21 S_D[23]
C21 S_D[24]
D20 S_D[25]
B21 S_D[26]
A22 S_D[27] / P_C[4]
C22 S_D[28] / P_C[3]
B22 S_D[29] / P_C[2]
A23 S_D[30] / P_C[1]
C23 S_D[31] / P_C[0]
A11 L_A[2]
B10 L_A[3]
C11 L_A[4]
A10 L_A[5]
D10 L_A[6]
B9 L_A[7]
C10 L_A[8]
A9 L_A[9]
B8 L_A[10]
A8 L_A[11]
C9 L_A[12]
B7 L_A[13]
D8 L_A[14]
A7 L_A[15]
C8 L_A[16]
B6 L_A[17]
A6 L_A[18]
C7 L_A[19] / OE[3]#
D5 L_OE[2]#
A5 L_OE[1]#
A3 L_OE[0]
D7 L_WE[3]#
E4 L_WE[2]#
B5 L_WE[1]#
C4 L_WE[0]#
C6 L_BWE[3]#
B4 L_BWE[2]#
A4 L_BWE[1]#
C5 L_BWE[0]#
B3 L_ADSC#
G4 L_CLK
B1 L_D[0]
C2 L_D[1]
C1 L_D[2]
D2 L_D[3]
D3 L_D[4]
D1 L_D[5]
E2 L_D[6]
E3 L_D[7]
E1 L_D[8]
F2 L_D[9]
F3 L_D[10]
F1 L_D[11]
G2 L_D[12]
G1 L_D[13]
G3 L_D[14]
H2 L_D[15]
H1 L_D[16]
H3 L_D[17]
J2 L_D[18]
J1 L_D[19]
K2 L_D[20]
J3 L_D[21]
K1 L_D[22]
K4 L_D[23]
L2 L_D[24]
K3 L_D[25]
L1 L_D[26]
M2 L_D[27]
M1 L_D[28]
L3 L_D[29]
N2 L_D[30]
M4 L_D[31]
AB3
AD2
AC3
AE3
AF3
AE4
AF2
AD1
AE7
AF6
AE21
AF21
AD20
AD21
AE23
AF23
AF22
AE22
AC24
AC25
AB25
AB24
AB26
AA26
Y26
W25
AA24
AA25
U24
T25
V2
U3
T0_LNK
T0_CRS
T0_COL
T0_FD
T0_LPBK
T0_TXD
T0_TXEN
T0_TXC
T0_RXC
T0_RXD
T1_LNK
T1_CRS
T1_COL
T1_FD
T1_LPBK
T1_TXD
T1_TXEN
T1_TXC
T1_RXC
T1_RXD
T2_LNK
T2_CRS
T2_COL
T2_FD
T2_LPBK
T2_TXD
T2_TXEN
T2_TXC
T2_RXC
T2_RXD
T3_LNK
T3_CRS
Output signals with programmable polarity.
Pin #
V1
V3
Y2
Y1
W1
W2
AC1
AC2
AF7
AD7
AE8
AE9
AF9
AE10
AD8
AF8
AF10
AD9
AE11
AD10
AF11
AD11
AE13
AF13
AF12
AE12
AE14
AD12
AF14
AD13
AE15
AE16
AD15
AF16
AF15
AD14
AD16
AE17
AF17
AE18
AD17
AF19
AD18
AE20
AE19
AF18
AD19
AF20
Signal Name
T3_COL
T3_FD
T3_LPBK
T3_TXD
T3_TXEN
T3_TXC
T3_RXC
T3_RXD
T4_LNK
T4_CRS
T4_COL
T4_FD
T4_LPBK
T4_TXD
T4_TXEN
T4_TXC
T4_RXC
T4_RXD
T5_LNK
T5_CRS
T5_COL
T5_FD
T5_LPBK
T5_TXD
T5_TXEN
T5_TXC
T5_RXC
T5_RXD
T6_LNK
T6_CRS
T6_COL
T6_FD
T6_LPBK
T6_TXD
T6_TXEN
T6_TXC
T6_RXC
T6_RXD
T7_LNK
T7_CRS
T7_COL
T7_FD
T7_LPBK
T7_TXD
T7_TXEN
T7_TXC
T7_RXC
T7_RXD
A25 T_MODE
U4 T_D[0]
U1 T_D[1]
T3 T_D[2]
U2 T_D[3]
R4 T_D[4]
T1 T_D[5]
R3 T_D[6]
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Pin #
T2
R1
P3
R2
N3
P1
P2
M3
N1
Signal Name
T_D[7]
T_D[8]
T_D[9]
T_D[10]
T_D[11]
T_D[12]
T_D[13]
T_D[14]
T_D[15]
D6
D11
D16
D21
F4
F23
L4
L23
T4
T23
AA4
AA23
AC6
AC11
AC16
AC21
A1
A2
A26
B2
B25
B26
C3
C24
D4
D9
D14
D19
D23
H4
J23
N4
P23
V4
W23
AC4
AC8
AC13
AC18
AC23
AD3
AD24
AE1
AE2
AE25
AF1
AF25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
© 1998 Zarlink Semiconductor, Inc.
7
Rev.2.1 – February, 1999







EA218EI6B equivalent, schematic
PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
EA218E
8-Port 10Mb Ethernet Access Controller
2.3 XpressFlow Bus Operation
Zarlink’s optimized XpressFlow Bus architecture
Provides 1.6G bps switching bandwidth
9 -33
1.07G bps
9 -40
1.28G bps
9 -50
1.6G bps
Full multi bus master structure
Allows XpressFlow Engine to communicate with Access Con-
trollers via a message passing protocol
9 Command Messages for passing control information be-
tween devices
9 Data Messages for forwarding an Ethernet frame from re-
ceiving port to transmission port
Built-in intelligent bus load regulator for data traffic balancing
Provides centralized bus arbitration with two level request pri-
orities
9 High priority for Data Messages
9 Low priority for Command Messages
2.3.1 Pin Description
Symbol
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
Type Name and Functions
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Note: During the system RESET period, Data Bit [31:28] are used as Processor Interface
Configuration bit [0:3]
Message Envelope – encompasses the entire period of a message transfer. Targets use the
leading edge of this signal to detect the beginning of a message transfer, and to decode the
message header for the intended target(s).
End of Frame – only used by frame data transfer messages to identify the end of frame condi-
tion. This signal is synchronous with the Rx Frame Status word appended to the end of the
message.
Initiator Ready – a normal true signal. When negated, it indicates the initiator had asserted wait
state(s) in between command words. Target should use this signal as enable signal for latching
the data from the bus.
CMOS Target Abort – when asserted, the target had aborted the reception of current message on the
I/O-OD bus.
CMOS High Priority Request – indicates one or more Bus Requester is requesting for high priority
I/O-OD message transfer.
CMOS Bus Request –Bus Request signals from Access Controller to Bus Access Arbitrator in Xpress-
Output Flow Engine
CMOS In- Bus Grant –Bus Grant signals from Bus Arbitrator to Bus Requester
put
CMOS Bus Overload – when asserted, all data forwarding bus bandwidth has been allocated. Cannot
Output support additional load for data forwarding traffic.
CMOS XpressFlow Bus Clock – 33MHz system clock
Input
© 1998 Zarlink Semiconductor, Inc.
15
Rev.2.1 – February, 1999










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