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零件编号 | FDN338 | ||
描述 | P-Channel Logic Level Enhancement Mode Field Effect Transistor | ||
制造商 | Fairchild Semiconductor | ||
LOGO | |||
1 Page
March 1998
FDN338P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
Features
-1.6 A, -20 V, RDS(ON) = 0.13 Ω @ VGS = -4.5 V
RDS(ON) = 0.18 Ω @ VGS = -2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
D
338
SuperSOTTM-3
G
S
D
GS
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain/Output Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDN338P
-20
±8
-1.6
-5
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
FDN338P Rev.D
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页数 | 4 页 | ||
下载 | [ FDN338.PDF 数据手册 ] |
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