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零件编号 | FDC634P | ||
描述 | P-Channel Enhancement Mode Field Effect Transistor | ||
制造商 | Fairchild Semiconductor | ||
LOGO | |||
1 Page
November 1997
FDC634P
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as cellular phone and
notebook computer power management and other battery
powered circuits where high-side switching, and low in-line
power loss are needed in a very small outline surface
mount package.
Features
-3.5 A, -20 V. RDS(ON) = 0.080 Ω @ VGS = -4.5 V
RDS(ON) = 0.110 Ω @ VGS = -2.5 V.
SuperSOTTM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
S
D
D .634
G
D
SuperSOT TM -6 pin 1 D
Absolute Maximum RatingsTA = 25°C unless otherwise note
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
16
25
34
FDC634P
-20
±8
-3.5
-11
1.6
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
FDC634P Rev.C
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页数 | 4 页 | ||
下载 | [ FDC634P.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
FDC634 | P-Channel Enhancement Mode Field Effect Transistor | Fairchild Semiconductor |
FDC634P | P-Channel Enhancement Mode Field Effect Transistor | Fairchild Semiconductor |
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