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PDF ( 数据手册 , 数据表 ) FDC37N972

零件编号 FDC37N972
描述 Advanced Notebook I/O Controller with Enhanced Keyboard Control and System Management
制造商 SMSC Corporation
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FDC37N972 数据手册, 描述, 功能
FDC37N972
ADVANCE INFORMATION
Advanced Notebook I/O Controller with Enhanced
Keyboard Control and System Management
FEATURES
!" 3.3V Operation With 5V Tolerant Buffers
!" ACPI 1.0 and PC99 Compliant
!" Three Power Planes
!" ACPI Embedded Controller Interface
!" Low Standby Current in Sleep Mode
!" Configuration Register Set Compatible With
ISA Plug-and-Play Standard (Version 1.0a)
!" Serial IRQ Interface Compatible With
Serialized IRQ Support for PCI Systems
!" Floppy Disk Interface on Parallel Port
!" 8051 Controller uses Parallel Port to
Reprogram the Flash ROM
!" Advanced Infrared Communications
Controller (IrCC 2.0)
- IrDA V1.1 (4Mbps), HPSIR, ASKIR,
Consumer IR Support
- Two IR Ports
- Relocatable Base I/O Address
!" 512k Byte Flash ROM Interface
- 8051/Host CPU Multiplexed Interface
- Sixteen 32K Pages - 8051 Keyboard
BIOS
- Eight 64K Pages - Host System BIOS
- Embedded Controller uses Parallel Port
to Reprogram Flash ROM
!" ISA Host Interface With Clock Run Support
and ACPI SCI Interface
- 16 Bit Address Qualification
- 8 Bit Data Bus
- Zero Wait-State I/O Register Access
- Shadowed Write Only registers
- IOCHRDY for ECP, IRCC 2.0 and Flash
Cycles
- 15 Direct IRQs Including nSMI
- Four 8 Bit DMA Channels
- XNOR Test Chain
!"High-Performance Embedded 8051
Keyboard and System Controller
- Provides System Power Management
- System Watch Dog Timer (WDT)
- 8042 Style Host Interface
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 2K Internal ROM, nEA Pin Select
- 32K Bank Switchable External Flash
ROM Interface
- 256 Bytes Data RAM
- On-Chip Control Registers Available via
MOVX External Data Access Commands
- Access to RTC and CMOS Registers
- Up to 16x8 Keyboard Scan Matrix
- Three 16 Bit Timer/Counters
- Integrated TX/RX Serial Interface
- Eleven 8051 Interrupt Sources
- Thirty-Two 8 Bit, Host/8051 Mailbox
Registers
- Thirty Maskable Hardware Wake-Up
Events Supported
- Fast GATEA20
- Fast CPU_RESET
- Multiple Clock Sources and Frequencies
- IDLE and SLEEP Modes
- Fail-Safe Ring Oscillator
!"Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two 128-Byte Banks
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format







FDC37N972 pdf, 数据表
EPP 1.7 DATA OR ADDRESS READ CYCLE.............................................................................353
ECP PARALLEL PORT TIMING..................................................................................................354
ACCESS.BUS TIMING..................................................................................................................358
HOST FLASH READ TIMING......................................................................................................359
HOST FLASH READ/WRITE .......................................................................................................361
ZERO WAIT STATE (NOWS) TIMING.......................................................................................363
FLASH PROGRAM FETCH TIMING...........................................................................................364
8051 FLASH READ TIMING ........................................................................................................365
8051 FLASH WRITE TIMING ......................................................................................................366
PS/2 CHANNEL RECEIVE TIMING DIAGRAM ........................................................................367
PS/2 CHANNEL TRANSMIT TIMING DIAGRAM.....................................................................369
PS/2 CHANNEL “BIT-BANG” TIMING ......................................................................................371
IN CIRCUIT TEST (ICT)................................................................................................................ 373
APPENDIX A................................................................................................................................... 377
HIGH-PERFORMANCE 8051 CYCLE TIMING AND INSTRUCTION SET.............................377
APPENDIX B................................................................................................................................... 382
HIGH PERFORMANCE 8051 EXTENDED INTERRUPT UNIT................................................382
8







FDC37N972 equivalent, schematic
TQFP
PIN#
186
187
188
189
190
191
141
142
145
146
147
140
139
204
206
NOTES
5
6
5
5
5
5, 8
5
1,
5
5
5
5
5
5
5
3,
5
NAME
GPIO2
(WK_SE04)
GPIO3
(TRIGGER)
GPIO4
(WK_SE07)/
KSO14
GPIO5
(WK_SE10)/
KSO15
GPIO6
(WK_SE11)/
IRMODE/IRR
X3A
GPIO7
(WK_SE06)5
GPIO8
(WK_SE12)/
IRRX2
GPIO9
(WK_SE13)/
IRTX2
GPIO10
(WK_SE14)/
IRMODE/IRR
X3B
GPIO11
(WK_SE15)/
AB2_DATA
GPIO12
(WK_SE16)/
AB2_CLK
GPIO14
(WK_SE20)
GPIO15
(WK_SE21)
GPIO16
(WK_SE22)5
GPIO17
(WK_SE23)/
GATEA20
DESCRIPTION
General Purpose I/O
General Purpose I/O (Interrupt 1
Event)
General Purpose I/O
Keyboard Scan Output
General Purpose I/O
Keyboard Scan Output
General Purpose I/O
FIR Mode Output or 2nd Receive
Input
General Purpose I/O
General Purpose I/O
IR Receive Input
General Purpose I/O
IR Transmit Output
General Purpose I/O
FIR Mode Output or 2nd Receive
Input
General Purpose I/O
ACCESS.bus 2 Serial Data
General Purpose I/O
ACCESS.bus 2 Clock
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
KBD GATEA20 Output
POWER
PLANE
VCC1
VCC1
VCC1
BUFFER
MODES2
IO8
IO8
IO8/OD8
VCC1
IO8/OD8
VCC1
IO8/(O8/I)
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
(IO8/IOD8)8
IO8/I
IO12/O12
IO8/O8/
(O8/I)
IO12/IOD12
IO12/IOD12
IO8
IO8
IO8
IO8/O8
16










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