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PDF ( 数据手册 , 数据表 ) FDC37CXFR

零件编号 FDC37CXFR
描述 Plug and Play Compatible Ultra I/O Controller with Fast IR
制造商 SMSC Corporation
LOGO SMSC Corporation LOGO 


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FDC37CXFR 数据手册, 描述, 功能
FDC37C93xFR
ADVANCE INFORMATION
Plug and Play Compatible Ultra I/OController
with Fast IR
FEATURES
5 Volt Operation
- Software and Register Compatible with
ISA Plug-and-Play Standard (Version 1.0a)
SMSC's Proprietary 82077AA
Compatible Register Set
Compatible Core
Soft Power Management, SMI Support
ACCESS.bus Support
8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 1µA Standby Current (typ)
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Four DMA Options
- Licensed CMOS 765B Floppy Disk
Controller
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Game Port Select Logic
- Supports Two Floppy Drives Directly
- 24mA AT Bus Drivers
- Low Power CMOS Design
Licensed CMOS 765B Floppy Disk
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48mA Drivers and Schmitt Trigger Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
Serial Ports
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte FIFOs
- Advanced Digital Data Separator







FDC37CXFR pdf, 数据表
PIN NO.
33
34
96
97
98
99
100
102
103
104
105
106
107
108
109
110
111:118
119
120
DESCRIPTION OF PIN FUNCTIONS
NAME
SYMBOL
SOFT POWER MANAGEMENT INTERFACE
Power On (Note 4)
nPowerOn
Button Input (Note 4)
Button_In
GENERAL PURPOSE I/O
GP I/O; IRQ in (Note 4)
GP10
GP I/O; IRQ in (Note 4)
GP11
GP I/O; WD Timer Output /IRRX (Note 4)
GP12
GP I/O; Power Led output /IRTX (Note 4)
GP13
GP I/O; GP Address Decode (Note 4)
GP14
GP I/O; GP Write Strobe (Note 4)
GP15
GP I/O; Joy Read Strobe/JOYCS (Note 4)
GP16
GP I/O; Joy Write Strobe (Note 4)
GP17
GP I/O; IDE2 Output Enable/8042 P20 (Note 4) GP20
GP I/O; Serial EEPROM Data In/AB_DATA (Note 4) GP21
GP I/O; Serial EEPROM Data Out/AB_CLK (Note 4) GP22
GP I/O; Serial EEPROM Clock (Note 4)
GP23
GP I/O; Serial EEPROM Enable (Note 4)
GP24
GP I/O; 8042 P21 (Note 4)
GP25
BIOS BUFFERS
ROM Bus (I/O to the SD Bus) (Note 4)
RD[0:7]
ROM Chip Select (only used for ROM) (Note 4)
nROMCS
ROM Output Enable (DIR) (only used for ROM) (Note 4) nROMDIR
BUFFER TYPE
I/O24
I/O24
I/O4
I/O4
I/O4
I/O24
I/O4
I/O4
I/O4
I/O4
I/O4
I/O8
I/O8
I/O4
I/O4
I/O4
I/O4
I
I
Note 0:
Note 1:
Note 2:
Note 3:
Note 4:
The interrupt request is output on one of the IRQx signals as 024 buffer type. If EPP or
ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.
In this case, the buffer type is OD24. Refer to the configuration section for more
information.
nCS -This pin is the active low chip select; it must be low for all chip accesses. For 12 bit
addressing, SA0:SA11, this input should be tied to GND. For 16 bit address qualification,
address bits SA12:SA15 can be "ORed" together and applied to this pin. If IDE2 is not
used, SA12 can be connected to nCS, pin 27 to SA13, pin 28 to SA14 and pin 29 to SA15
nYY - The "n" as the first letter of a signal name indicates an "Active Low" signal
nHDCS2 and nHDCS3 require a pull-up to ensure a logic high at power-up when used for
IDE2 until the Active Bit is set to 1.
See Table 1, Multifunction Pins with GPI/O and Other Alternate Functions.
8







FDC37CXFR equivalent, schematic
STATUS REGISTER A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state
of the FINTR pin and several disk interface
pins in PS/2 and Model 30 modes. The SRA can
be accessed at any time when in PS/2 mode. In
the PC/AT mode the data bus pins D0-D7 are
held in a high impedance state for a read of
address 3F0.
PS/2 Mode
RESET
COND.
7
INT
PENDING
0
65432
nDRV2 STEP nTRK0 HDSEL nINDX
N/A 0 N/A 0 N/A
1
nWP
N/A
0
DIR
0
BIT 0 DIRECTION
Active high status indicating the direction of
head movement. A logic "1" indicates inward
direction; a logic "0" indicates outward direction.
BIT 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk
interface input. A logic "0" indicates that the disk
is write protected.
BIT 2 nINDEX
Active low status of the INDEX disk interface
input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface
input. A logic "1" selects side 1 and a logic "0"
selects side 0.
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface
input.
BIT 5 STEP
Active high status of the STEP output disk
interface output pin.
BIT 6 nDRV2
Active low status of the DRV2 disk interface
input pin, indicating that a second drive has
been installed.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy
Disk Interrupt output.
16










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