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PDF ( 数据手册 , 数据表 ) FDC37C93

零件编号 FDC37C93
描述 Plug and Play Compatible Ultra I/O Controller with Soft Power Management
制造商 SMSC Corporation
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FDC37C93 数据手册, 描述, 功能
FDC37C93xAPM
ADVANCE INFORMATION
Plug and Play Compatible Ultra I/O™ Controller
with Soft Power Management
FEATURES
5 Volt Operation
ISA Plug-and-Play Standard (Version 1.0a)
Compatible Register Set
Soft Power Management, SMI Support
ACPI/Legacy Support
- SCI/SMI Support
- Power Management Timer
- Power Button Override Event
- Either Edge Triggered Interrupts
ACCESS.bus Support
8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 1 µA Standby Current (typ)
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Four DMA Options
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Game Port Select Logic
- Supports Two Floppy Drives Directly
- 24mA AT Bus Drivers
- Low Power CMOS Design
Licensed CMOS 765B Floppy Disk
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48mA Drivers and Schmitt Trigger Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
Serial Ports
- Relocatable to 480 Different Addresses







FDC37C93 pdf, 数据表
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
154
153
23
24
25
30
31
26
27
28
29
138:131
140
141
143
144
128
129
127
126
142
122
124
121
91
NAME
SYMBOL
Data Carrier Detect 2 (Note 4)
nDCD2
Ring Indicator 2 (Note 4)
nRI2
IDE1 INTERFACE
IDE1 Enable (Note 4)
nIDE1_OE
IDE1 Chip Select 0 (Note 4)
nHDCS0
IDE1 Chip Select 1 (Note 4)
nHDCS1
IOR Output (Note 4)
nIOROP
IOW Output (Note 4)
nIOWOP
IDE1 Interrupt Request (Note 4)
IDE1_IRQ
IDE2 INTERFACE
IDE2 Chip Select 2/SA13 (Note 3, 4)
nHDCS2
IDE2 Chip Select 3/SA14 (Note 3, 4)
nHDCS3
IDE2 Interrupt Request/SA15 (Note 4)
IDE2_IRQ
PARALLEL PORT INTERFACE
Parallel Port Data Bus
PD[0:7]
Printer Select
nSLCTIN
Initiate Output
nINIT
Auto Line Feed
nALF
Strobe Signal
nSTB
Busy Signal
BUSY
Acknowledge Handshake
nACK
Paper End
PE
Printer Selected
SLCT
Error at Printer
nERROR
REAL-TIME CLOCK
32 Khz Crystal Input
XTAL1
32 Khz Crystal Output
XTAL2
Battery Voltage
Vbat
KEYBOARD/MOUSE
Keyboard Data
KDAT
BUFFER
TYPE
I
I
O4
O24
O24
O24
O24
I
I/O24
I/O24
I
I/O24
OD24/O24
OD24/O24
OD24/O24
OD24/O24
I
I
I
I
I
ICLK2
OCLK2
I/OD16P
8







FDC37C93 equivalent, schematic
FLOPPY DISK CONTROLLER
FDC INTERNAL REGISTERS
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and
the floppy disk drives. The FDC integrates the
functions of the Formatter/Controller, Digital
Data Separator, Write Precompensation and
Data Rate Selection logic for an IBM XT/AT
compatible FDC. The true CMOS 765B core
guarantees 100% IBM PC XT/AT compatibility
in addition to providing data overflow and
underflow protection.
The Floppy Disk Controller contains eight
internal registers which facilitate the interfacing
between the host microprocessor and the disk
drive. Table 2 shows the addresses required to
access these registers. Registers other than the
ones shown are not supported. The rest of the
description assumes that the primary addresses
have been selected.
The FDC is compatible to the 82077AA using
SMSC's proprietary floppy disk controller core.
PRIMARY
ADDRESS
3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7
Table 2 - Status, Data and Control Registers
(Shown with base addresses of 3F0 and 370)
SECONDARY
ADDRESS
R/W
REGISTER
370 R Status Register A (SRA)
371 R Status Register B (SRB)
372 R/W Digital Output Register (DOR)
373 R/W Tape Drive Register (TSR)
374 R Main Status Register (MSR)
374 W Data Rate Select Register (DSR)
375 R/W Data (FIFO)
376 Reserved
377 R Digital Input Register (DIR)
377 W Configuration Control Register (CCR)
16










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