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PDF ( 数据手册 , 数据表 ) FC106

零件编号 FC106
描述 Fibre Channel Transceiver 1.0625 GBaud
制造商 STMicroelectronics
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FC106 数据手册, 描述, 功能
® FC106
Fibre Channel Transceiver 1.0625 GBaud
FEATURES
s Serial Link Transceiver
q serializer and deserializer
q implementing the Fibre Channel FC0
and FC1 layers
s Direct support for 1.0625 GBaud Fibre
Channel (ANSI X3.230-1994) rates
s Fibre Channel 10-bit Interface (ANSI
TR/X3.18-199X)
s Direct interfaces to optical tranceivers
s Plesiochronous mode operation
q transmitter and receiver clock
frequencies may differ by up to 100 ppm
s Integrated Fibre Channel 8b/10b
encode/decode (optional use through
JTAG)
s Byte and word synchronization of
incoming serial stream
s Supports any DC-balanced encoding
scheme
s Internal Loop-Back for Self-Test
s Random Pattern Auto-Test
s Optional integrated impedance
adaptation to transmission line
characteristics (50 or 75 ohms)
s TTL compatible parallel I/O’s
s JTAG Test Access Port
s 0.35µ CMOS Technology for low cost
and low power
s PQFP package available in two sizes:
14x14 mm (FC106/14) or 10x10 mm
(FC106/10)
PRELIMINARY DATA
Receive
Byte
Clock
Parallel Interface
REFCLK
10 bits
8 bit / 10 bit
DECODER
(optional)
8 bit / 10 bit
ENCODER
(optional)
DESER IALIZER
CLOCK RECOVERY
BYTE AND WORD
ALIGNEMENT
SERIALI ZER
AND CLOCK
FREQ UENCY
MULTIPLIC ATION
FC 106
1.0625 Gbaud
Serial data over copper
or optical cables
APPLICATIONS
s Fibre Channel Arbitrated Loop
s Fibre Channel fabric
s Transmission schemes encoding
bytes as 10-bit characters to form a
DC-balanced stream
s High performance backplane
interconnect
1/32
September 98
Revision 1.2







FC106 pdf, 数据表
FC106
3.1 Block diagram
Figure 3.1
TCK(*)
TRSTN(*)
TMS(*)
TDI(*)
TDO(*)
TEST ENABLE(*)
TX [0:9]
Block diagram
JTAG
CONTROL
ENC
SERIALIZER
XOR
Tree
TX-
t ransmitter
TX+
RCB[0:1]
AT (*)
RS (*)
REFCLK
SELF
TEST
ENC
RX[0:9]
8b/10b
encoder
DLL clock generator
Clock Recovery
ZC
s etting
ZC+(*)
ZC-(*)
8b/10b
decoder
Word
Align-
ment
Bit
Align-
ment
RX-
rece iver
EN_CDET
DESERIALIZER
COM_DET
RX+
(*)Test signals not
included in FCS
10-bit interface
EWRAP
3.2 Input latches
The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0:9]. The user-provided
reference clock signal REFCLK is also used as the transmit byte clock. The TX[0:9] and
REFCLK signals must be properly aligned, as shown in Section 6.1: Transmit interface
timing and latency on page 20.
8/32
September 98
Revision 1.2







FC106 equivalent, schematic
FC106
4 Serial I/O Electrical Model
This simplified model is given for typical board simulation, within 15% precision. The
termination at the receiving end can be either internal or external, following Section 3.13.
Figure 4.1
Serial I/O electrical schematic diagram
Vss
Tr
Vdd Tr = Tf = 0.2nS
R1 1pF
1pF
Vdd
Tf
R1
Vss
Simplified serial
transmitter model
Rout
Zc = 40
Td = 0.15nS
Zc = 40
Td = 0.15nS
Simplified QFP64
package model
0.01µF(optional)
Zc = 60
Td = 0.15nS
Rc
Your board and/or
cable/connector model
0.01µF(optional)
Zc = 60
Td = 0.15nS
Simplified QFP64
package model
0.5pF 0.5pF
Rin
Simplified serial
receiver model
1.5K1.5K
1.5K1.5K
TO DESERIALIZER
PARAMETER VALUES
FOR TYPICAL
SIMULATIO N
R1
Rout
Rc
Rin
16/32
September 98
50CONFIGURATI ON
100
200
100if external termination
100if internal termination
Revision 1.2
75CONFIGURA TION
150
300
150if external termination
150if internal termination










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