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PDF ( 数据手册 , 数据表 ) FIN1215MTD

零件编号 FIN1215MTD
描述 LVDS 21-Bit Serializers/De-Serializers
制造商 Fairchild Semiconductor
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FIN1215MTD 数据手册, 描述, 功能
October 2003
Revised October 2004
FIN1217 FIN1218
FIN1215 FIN1216
LVDS 21-Bit Serializers/De-Serializers
General Description
The FIN1217 and FIN1215 transform 21-bit wide parallel
LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 21 bits of input LVTTL data are sampled and trans-
mitted.
The FIN1218 and FIN1216 receive and convert the 3 serial
LVDS data streams back into 21 bits of LVTTL data. Refer
to Table 1 for a matrix summary of the Serializers and De-
serializers available. For the FIN1217, at a transmit clock
frequency of 85 MHz, 21 bits of LVTTL data are transmitted
at a rate of 595 Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and
cable size problems associated with wide and high-speed
TTL interfaces.
Features
s Low power consumption
s 20 MHz to 85 MHz shift clock support
s 50% duty cycle on the clock output of receiver
s ±1V common-mode range around 1.2V
s Narrow bus reduces cable size and cost
s High throughput (up to 1.785 Gbps throughput)
s Up to 595 Mbps per channel
s Internal PLL with no external component
s Compatible with TIA/EIA-644 specification
s Devices are offered in 48-lead TSSOP packages
Ordering Code:
Order Number Package Number
Package Description
FIN1215MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1216MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1217MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1218MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation DS500876
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FIN1215MTD pdf, 数据表
Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 15)
Symbol
Parameter
Test Conditions
LVTTL/CMOS DC Characteristics
VIH
VIL
VOH
VOL
VIK
IIN
IOFF
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Clamp Voltage
Input Current
Input/Output Power Off Leakage Current
IOH = −0.4 mA
IOL = 2 mA
IIK = −18 mA
VIN = 0V to 4.6V
VCC = 0V,
All LVTTL Inputs/Outputs 0V to 4.6V
IOS Output Short Circuit Current
Receiver LVDS Input Characteristics
VOUT = 0V
VTH
VTL
VICM
IIN
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Common Mode Range
Input Current
Receiver Supply Current
Figure 2, Table 2
Figure 2, Table 2
Figure 2, Table 2
VIN = 2.4V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
ICCWR
3:21 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 16)
CL = 8 pF,
See Figure 3
33.0 MHz
40.0 MHz
65.0 MHz
(85.0 MHz Specification for FIN1218 only)
85.0 MHz
Min
2.0
GND
2.7
10.0
100
0.05
Typ
3.3
60.0
56.0
75.0
92.0
Max Units
VCC
0.8
0.3
1.5
10.0
±10.0
120
V
V
V
V
V
µA
µA
mA
100
2.35
±10.0
±10.0
mV
mV
V
µA
µA
66.0
74.0
102
125
mA
ICCPDR Powered Down Supply Current
PwrDn = 0.8V (RxOut stays LOW)
NA 400 µA
Note 15: All Typical Values are at TA = 25°C and with VCC = 3.3V. Positive current values refer to the current flowing into device and negative values means
current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except VOD and VOD).
Note 16: The power supply current for the receiver can be different with the number of active I/O channels.
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FIN1215MTD equivalent, schematic
AC Loading and Waveforms (Continued)
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter ±3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right +when data is HIGH (by switching between
CLK1 and CLK2 in Figure 11)
The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise
(VCC noise frequency <2 MHz).
FIGURE 19.
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