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PDF ( 数据手册 , 数据表 ) M2087

零件编号 M2087
描述 VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
制造商 Integrated Circuit Solution Inc
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M2087 数据手册, 描述, 功能
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n M2080/81/82
M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
Integrated SAW delay line; Output of 15 to 700 MHz *
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
LVPECL clock output (CML and LVDS options available)
Pin-selectable PLL divider ratios support FEC ratios
• M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 M 2 0 8 0
31
32 S e r i e s
16
15
14
33 13
34 ( T o p V i e w ) 12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Output Clock
(either output)
MHz
1/1
237/255
238/255
622.0800
666.5143
669.3266
622.08
or
155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
M2080 Series
MUX
0 Rfec
Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL Phase
Detector
Mfec Div
2
FEC_SEL1:0
2
FIN_SEL1:0
3
P_SEL2:0
Mfec / Rfec Divider
LUT
Mfin Divider
LUT
Loop Filter
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
VCSO
P Divider
(1, 4, 8, 32 or TriState)
Tri-state
P Divider
LUT
Figure 2: Simplified Block Diagram
LOL
FOUT
nFOUT
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
Revised 30Jul2004
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400







M2087 pdf, 数据表
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Preliminary Information
Optional Hitless Switching and Phase Build-out
The M208x Series is available with a Hitless Switching
feature that is enabled during device manufacturing.
In addition, a Phase Build-out feature is also offered.
These features are offered as device options and are
specified by device order code. Refer to “Ordering
Information” on pg. 14.
The Hitless Switching feature (with or without Phase
Build-out) is designed for applications where switching
occurs between two stable system reference clocks. It
should not be used in loop timing applications, or when
reference clock jitter is greater than 1 ns pk-pk. The
Hitless Switching sequence is triggered by the LOL
circuit, which is activated by a 4 ns phase transient. This
magnitude of phase transient can generated by the
CDR (Clock & Data Recovery unit) in loop timing mode,
especially during a system jitter tolerance test. It can
also be generated by some types of Stratum clock
DPLLs (digital PLL), especially those that do not include
a post de-jitter APLL (analog PLL).
When the M208x Series is operating in wide bandwidth
mode (NBW=0), the optional Hitless Switching function
puts the device into narrow bandwidth mode when
during the Hitless Switching sequence. This allows the
PLL to lock the new input clock phase gradually. With
proper configuration of the external loop filter, the output
clock phase change complies with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
The optional proprietary Phase Build-out (PBO)
function enables the PLL to absorb most of the phase
change of the input clock during reference switching.
The PBO function selects a new VCSO clock edge for
the PLL Phase Detector feedback clock, selecting the
edge closest in phase to the new input clock phase.
This reduces re-lock time, the generation of wander,
and extra output clock cycles.
The Hitless Switching and Phase Build-out functions
are triggered by the LOL circuit. For proper operation,
a low phase detector frequency must be avoided. See
“Guidelines for Using LOL” on pg. 6 for information
regarding the phase detector frequency.
HS/PBO Operation
Once triggered, the following HS/PBO sequence
occurs:
1. The HS function disables the PLL Phase Detector
and puts the device into NBW (narrow bandwidth)
mode. The internal resistor Rin is changed to
2100k. See the Narrow Bandwidth (NBW) Control
Pin on pg. 8.
2. If included, the PBO function adds to (builds out) the
phase in the clock feedback path (in VCSO clock
cycle increments) to align the feedback clock with
the (new) reference clock input phase.
3. The PLL Phase Detector is enabled, allowing the
PLL to re-lock.
4. Once the PLL Phase Detector feedback and input
clocks are locked to within 2 nsec for 8 consecutive
cycles, a timer (WBW timer) for resuming wide
bandwidth (in 175 nsec) is started.
5. When the WBW timer times out, the device reverts
to wide loop bandwidth mode (i.e., Rin is returned to
100k) and the HS/PBO function is re-armed.
The LOL pin will indicate lock status on a cycle-to-cycle
basis and may be intermittent until PLL phase lock has
fully stabilized.
Narrow Bandwidth (NBW) Control Pin
A Narrow Loop Bandwidth control pin (NBW pin) is
included to enable adjustment of the PLL loop
bandwidth. In wide bandwidth mode (NBW=0), the
internal resistor Rin is 100k. With the NBW pin
asserted (NBW=1), the internal resistor Rin is changed to
2100k. This lowers the loop bandwidth by a factor of
about 21 (2100 / 100) and lowers the damping factor by
about 4.6 (the square root of 21), assuming the same
external loop filter component values.
HS/PBO Sequence Trigger Mechanism
The HS function (or the combined HS/PBO function)
is armed after the device locks to the input clock refer-
ence. Once armed, HS is triggered by the occurance of
a Loss of Lock condition. This would typically occur as a
consequence of a clock reference failure, a clock failure
upstream to the M208x Series, or a M208x Series clock
reference mux reselection.
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
8 of 14
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400














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