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PDF ( 数据手册 , 数据表 ) M2020

零件编号 M2020
描述 VCSO BASED CLOCK PLL
制造商 Integrated Circuit Systems
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M2020 数据手册, 描述, 功能
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2020/21
VCSO BASED CLOCK PLL
GENERAL DESCRIPTION
The M2020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M2020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
Output frequencies of 15 to 700 MHz *
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW pin)
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available for SONET (GR-253) /
SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
Industrial temperature grade available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M2020
32 M 2 0 2 1
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2020-11-622.0800 or M2021-11-622.0800
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(M2020)
(M2021)
19.44 or 38.88
(M2020) (M2021)
32 or 16
77.76
155.52
8 622.08
4
622.08
1
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
LOL
M2020/21
Loop
Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL1:0 2
FIN_SEL1:0 2
P_SEL2:0 3
MUX
0 R Div
(1, 4,
16, 64)
1
Phase
Detector
VCSO
M / R Divider
LUT
M Divider
(1, 4, 16, 64)
Mfin Div
(1, 4, 8, 32) or
( 1, 4, 8, 16)
Mfin Divider
LUT
P Divider
TriState
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
P Divider
LUT
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 2: Simplified Block Diagram
M2020/21 Datasheet Rev 1.0
Revised 30Jul2004
M2020/21 VCSO Based Clock PLL
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400







M2020 pdf, 数据表
Integrated
Circuit
Systems, Inc.
M2020/21
VCSO BASED CLOCK PLL
Product Data Sheet
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50to VCC - 2V
Symbol Parameter
Min Typ Max Unit Conditions
Power Supply VCC Positive Supply Voltage
3.135 3.3 3.465 V
ICC Power Supply Current
175 225 mA
All
Differential
Inputs
VP-P
VCMR
CIN
Peak to Peak Input Voltage
Common Mode Input
Input Capacitance
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
0.15
0.5
V
Vcc - .85 V
4 pF
Differential
Inputs with
Pull-down
IIH Input High Current (Pull-down)
IIL Input Low Current (Pull-down) DIF_REF0, DIF_REF1
Rpulldown Internal Pull-down Resistance
150 µA
VCC = VIN =
-5 µA 3.456V
50 k
Differential
Inputs
Biased to
VCC/2
IIH
IIL
Rbias
Input High Current (Biased)
Input Low Current (Biased)
Biased to Vcc/2
nDIF_REF0, nDIF_REF1
150
-150
See Figure 4
µA
µA
k
VIN =
0 to 3.456V
All LVCMOS
/ LVTTL
Inputs
VIH
VIL
CIN
Input High Voltage
Input Low Voltage
Input Capacitance
REF_SEL, FIN_SEL1, FIN_SEL0, 2
MR_SEL1, MR_SEL0, P_SEL2, -0.3
P_SEL1, P_SEL0, NBW
Vcc + 0.3 V
0.8 V
4 pF
LVCMOS /
LVTTL
Inputs with
Pull-down
IIH Input High Current (Pull-down) REF_SEL, FIN_SEL1, FIN_SEL0,
IIL
Input Low Current (Pull-down) MR_SEL1, MR_SEL0, P_SEL2,
P_SEL1, P_SEL0
Rpulldown Internal Pull-down Resistance
-5
150 µA
µA
VCC = VIN =
3.456V
50 k
LVCMOS /
LVTTL
Inputs with
Pull-UP
IIH
IIL
Rpullup
Input High Current (Pull-UP)
Input Low Current (Pull-UP)
Internal Pull-UP Resistance
NBW
-150
50
5 µA
µA
VCC = 3.456V
VIN = 0 V
k
Differential
Outputs
LVCMOS
Output
VOH
VOL
VP-P
VOH
VOL
Output High Voltage
FOUT0, nFOUT0,
Output Low Voltage
FOUT1, nFOUT1
Peak to Peak Output Voltage 1
Output High Voltage
Output Low Voltage
LOL
Vcc - 1.4
Vcc - 2.0
0.4
2.4
GND
Vcc - 1.0 V
Vcc - 1.7 V
0.85 V
VCC V
0.4 V
IOH= 1mA
IOL= 1mA
Note 1: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 9.
Table 10: DC Characteristics
M2020/21 Datasheet Rev 1.0
8 of 10
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400














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