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零件编号 | M2006-12A-622.0800 | ||
描述 | VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING | ||
制造商 | Integrated Circuit Systems | ||
LOGO | |||
1 Page
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING
GENERAL DESCRIPTION
The M2006-12A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
Clock multiplication ratios (including
forward and inverse FEC) are
pin-selected from pre-programming
look-up tables. Includes Hitless
Switching and Phase Build-out to
enable SONET (GR-253) / SDH (G.813) MTIE and
TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater
clock phase change is detected.
This phase-change triggered implementation of HS is
not recommended when using an unstable reference
(more than 1ns jitter pk-to-pk) or when the resulting
phase detector frequency is less than 5MHz.
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 2 0 0 6 - 1 2 A 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
FEATURES
◆ Reduced intrinsic output jitter and improved power
supply noise rejection compared to M2006-12
◆ Similar to the M2006-02A - and pin-compatible - but
adds Hitless Switching and Phase Build-out functions
◆ Includes APC pin for Phase Build-out function (for
absorption of the input phase change)
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation
◆ Input reference and VCSO frequencies up to 700MHz
(Specify VCSO frequency at time of order)
◆ Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Commercial and Industrial temperature grades
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Combinations
Using M2006-12A-622.0800
PLL Ratio Input Clock (MHz) Output Clock (MHz)
1/1
237/255
(inverse FEC)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
622.08
or
155.52
Table 1: Example I/O Clock Combinations Using M2006-12A-622.0800
Using M2006-12A-669.3266
PLL Ratio Input Clock (MHz) Output Clock (MHz)
237/255
(FEC rate)
1/1
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-12A-669.3266
SIMPLIFIED BLOCK DIAGRAM
M2006-12A
Loop
Filter
APC
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
0
Rfec Div
1
VCSO
Mfec Div
Mfin Div
(1, 4, 8, or 32)
P0 Div
(1 or 4)
FOUT0
nFOUT0
4
FEC_SEL3:0
2
FIN_SEL1:0
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
P1 Div
(1 or 4)
FOUT1
nFOUT1
P0_SEL
Figure 2: Simplified Block Diagram
P1_SEL
M2006-12A Datasheet Rev 1.0
Revised 28Jul2004
M2006-12A VCSO Based FEC Clock PLL with Hitless Switching
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Min Typ
Max Unit Test Conditions
Input
Frequency
Range
FIN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700 MHz
Output
FFOUT Output Frequency
Frequency
Range
APR VCSO Pull-Range
PLL Loop
Constants 1
Phase Noise
and Jitter
KVCO
RIN
BWVCSO
Φn
J(t)
tPW
tR
tF
VCO Gain
Internal Loop Resistor
VCSO Bandwidth
Single Side Band
Phase Noise
@622.08MHz
Jitter (rms)
@622.08MHz
Output Duty Cycle 2
FOUT0, nFOUT0,
FOUT1, nFOUT1
Output Rise Time 2
Output Fall Time 2
FOUT0, nFOUT0,
FOUT1, nFOUT1
Commercial
Industrial
1kHz Offset
10kHz Offset
100kHz Offset
12kHz to 20MHz
50kHz to 80MHz
P0, P1 = 1
P0, P1 = 4
FOUT0, nFOUT0,
FOUT1, nFOUT1
100
±120
±50
40
45
200
200
±200
±150
800
50
700
-72
-94
-123
0.25
0.25
50
50
450
450
700
0.5
0.5
60
55
500
500
Note 1: Parameters needed for PLL Simulator software; see PLL Simulator Tool Available on pg. 5.
Note 2: See Parameter Measurement Information on pg. 8.
MHz
ppm
ppm
kHz/V
kΩ
kHz
dBc/Hz
Fin=19.44 MHz
dBc/Hz Mfin=32, Mfec=1, Rfec=1
dBc/Hz
ps rms
ps rms
%
%
ps 20% to 80%
ps 20% to 80%
Table 12: AC Characteristics
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
20%
Clock Output
80%
tR
80%
VP-P
20%
tF
Figure 5: Output Rise and Fall Time
FOUT
odc =
tPW
tPERIOD
tPW
(Output Pulse Width)
tPERIOD
Figure 6: Output Duty Cycle
M2006-12A Datasheet Rev 1.0
8 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
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页数 | 10 页 | ||
下载 | [ M2006-12A-622.0800.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
M2006-12A-622.0800 | VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING | Integrated Circuit Systems |
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