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PDF ( 数据手册 , 数据表 ) M1040-11I156.2500

零件编号 M1040-11I156.2500
描述 VCSO BASED CLOCK PLL WITH AUTOSWITCH
制造商 Integrated Circuit Systems
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M1040-11I156.2500 数据手册, 描述, 功能
Integrated
Circuit
Systems, Inc.
Preliminary Information
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Loss of Lock (LOL) indicator output
Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M1040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R Div
LOL
Phase
Detector
M / R Divider
LUT
PLL
Phase
Detector
M Divider
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL1
MR_SEL0
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44
77.76
155.52
622.08
8 155.52
2 or
1 77.76
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
VCSO
P Divider
(1 or 2)
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400







M1040-11I156.2500 pdf, 数据表
Integrated
Circuit
Systems, Inc.
Power-Up Initialization Function (INIT Pin)
The initialization function provides a short-term override
of the narrow bandwidth mode when the device is
powered up in order to facilitate phase locking.
When INIT is set to logic 1, initialization is enabled. With
NBW set to logic 1 (narrow bandwidth mode), the
initialization function puts the PLL into wide bandwidth
mode until eight consecutive phase detector cycles
occur without a single LOL event. Once the eight valid
PLL locked states have occurred, the PLL bandwidth is
automatically reduced to narrow bandwidth mode.
When INIT is logic 0, the device is forced into wide
bandwidth mode unconditionally.
External Loop Filter
The M1040 requires the use of an external loop filter
components. These are connected to the provided filter
pins (see Figure 5).
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Because of the differential signal path design, the
implementation consists of two identical
complementary RC filters as shown in
Figure 5.
RLOOP CLOOP
RPOST
RLOOP CLOOP
RPOST
CPOST
CPOST
OP_IN nOP_IN
49
OP_OUT nOP_OUT nVC VC
85
67
Figure 5: External Loop Filter
PLL bandwidth is affected by the total “M” (feedback
divider) value, loop filter component values, and other
device parameters. See Table 6, Example External
Loop Filter Component Values, below.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
Example External Loop Filter Component Values1
for M1040-yz-155.5200
VCSO Parameters: KVCO = 200kHz/V, RIN = 100k(pin NBW = 0), VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Comp. Values Nominal Performance Using These Values
FREF
(MHz)
FVCSO
(MHz)
MR_SEL2:0 MDiv NBW
RLOOP
CLOOP
RPOST
CPOST
PLL Loop Damping Passband
Bandwidth Factor Peaking (dB)
19.44 2 155.52
000 8 0
6.8k10µF
82k1000pF
315Hz
5.4 0.07
77.76 3 155.52
010 2 0
3.9k10µF
33k1000pF
715Hz
6.2 0.05
77.76 2 155.52
0 1 1 16 0
12k2.2µF 82k1000pF
275Hz
3.1 0.20
155.52 3 155.52
100 1 0
2.7k10µF
47k470pF
980Hz
6.0 0.05
155.52 2 155.52
101 8 0
5.6k4.7µF 82k1000pF
260Hz
3.0 0.20
Table 6: Example External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: Optimal for system clock filtering.
Note 3: Optimal for loop timing mode (LOL or Hitless Switching should not be used).
M1040 Datasheet Rev 0.1
8 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400














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