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PDF ( 数据手册 , 数据表 ) 37LV36-ISN

零件编号 37LV36-ISN
描述 36K/ 64K/ and 128K Serial EPROM Family
制造商 Microchip Technology
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37LV36-ISN 数据手册, 描述, 功能
37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
• Operationally equivalent to Xilinx® XC1700 family
• Wide voltage range 3.0 V to 6.0 V
• Maximum read current 10 mA at 5.0 V
• Standby current 100 µA typical
• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
• Full Static Operation
• Sequential Read/Program
• Cascadable Output Enable
• 10 MHz Maximum Clock Rate @ 5.0 Vdc
• Programmable Polarity on Hardware Reset
• Programming with industry standard EPROM pro-
grammers
• Electrostatic discharge protection > 4,000 volts
• 8-pin PDIP/SOIC and 20-pin PLCC packages
• Data Retention > 200 years
• Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V VCC range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device Bits Programming Word
37LV36
37LV65
37LV128
36,288
65,536
131,072
1134 x 32
2048 x 32
4096 x 32
Xilinx is a registered trademark of Xilinx Corporation.
PACKAGE TYPES
PDIP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 VPP
6 CEO
5 VSS
SOIC
DATA
CLK
RESET/OE
CE
PLCC
18
27
36
45
DATA VCC
VCC
VPP
CEO
VSS
CLK 4
5
RESET/OE 6
7
CE 8
18
17 VPP
16
15
14 CEO
Vss
BLOCK DIAGRAM
CE
RESET/OE
CEO
ADDRESS EPROM
Counter ARRAY
CLK
OE
DATA
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21109E-page 1







37LV36-ISN pdf, 数据表
37LV36/65/128
FIGURE 11-3: ENTER AND EXIT PROGRAMMING MODES
Enter Mode
Exit Mode
VCC
VPP
VPP2
CLK
VCCP
VPP1
TRPP
TSVC
TFPP
THVC
DATA
CE
RESET/OE
TSVCE
TSVOE
TSVC
VPP
VCC
CE
RESET/OE
CLK
VPP2
VCCP
1 ms
VSS
VSS
VSS
VSS
VSS
FIGURE 11-4: PROGRAMMING CYCLE OVERVIEW (NO VERIFY UNTIL ENTIRE ARRAY IS
PROGRAMMED)
VCC
VPP
CLK
CE
VCC = VCCP
VPP1
VPP = VPP2
Enter
500 µs
Programming Programming
Mode
Mode
500 µs
Programming
Mode
500 µs
Programming
Mode
500 µs
Programming
Mode
2 CLKS
**Load
Word 1
CE low to clear
data latches
**Load
Word 2
**Load
Word 3
**Load
Word 4
**Load
Word 5
Clock Increments
Address Counter
RESET/OE
CEO
High if RESET/OE configured
**
**
*
** 32 Clocks
Low if RESET/OE configured
*Note: The CEO pin is high impedance when VPP = VPP1
FIGURE 11-5: DETAILS OF PROGRAM CYCLE
V PP
Clear PROM
Internal Data
Latches
Load PROM
Internal
Data Latches
TRPP TFPP
TPGM
CLK
DATA
CE
RESET/OE
*
TLCE
TSDP
1
TSCC
THDP
2
*Note: The programmer must float the data pin while
CE is low to avoid bus contention
32 (Last Bit)
TSIC
THIC
THOV
Program
Pulse
Increment
Word
Counter
DS21109E-page 8
© 1996 Microchip Technology Inc.














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