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PDF ( 数据手册 , 数据表 ) 30151-33

零件编号 30151-33
描述 Geode GXm Processor Integrated x86 Solution with MMX Support
制造商 National Semiconductor
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30151-33 数据手册, 描述, 功能
April 2000
Geode™ GXm Processor
Integrated x86 Solution with MMX Support
General Description
The National Semiconductor® Geode™ GXm processor
is an advanced 32-bit x86 compatible processor offering
high performance, fully accelerated 2D graphics, a 64-bit
synchronous DRAM controller and a PCI bus controller,
all on a single chip that is compatible with Intel’s MMX
technology.
The GXm processor core is a proven design that offers
competitive CPU performance. It has integer and floating
point execution units that are based on sixth-generation
technology. The integer core contains a single, six-stage
execution pipeline and offers advanced features such as
operand forwarding, branch target buffers, and extensive
write buffering. A 16 KB write-back L1 cache is accessed
in a unique fashion that eliminates pipeline stalls to fetch
operands that hit in the cache.
In addition to the advanced CPU features, the GXm pro-
cessor integrates a host of functions which are typically
implemented with external components. A full-function
graphics accelerator provides pixel processing and ren-
dering functions.
A separate on-chip video buffer enables >30 fps MPEG1
video playback when used together with the CS5530 I/O
companion chip. Graphics and system memory accesses
are supported by a tightly-coupled synchronous DRAM
(SDRAM) memory controller. This tightly coupled memory
subsystem eliminates the need for an external L2 cache.
The GXm processor includes Virtual System Architec-
ture® (VSA™ technology) enabling XpressGRAPHICS
and XpressAUDIO subsystems as well as generic emula-
tion capabilities. Software handler routines for the Xpress-
GRAPHICS and XpressAUDIO subsystems can be
included in the BIOS and provide compatible VGA and 16-
bit industry standard audio emulation. XpressAUDIO tech-
nology eliminates much of the hardware traditionally asso-
ciated with audio functions.
Geode™ GXm Processor Internal Block Diagram
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
Internal Bus Interface Unit
X-Bus
FPU
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
SDRAM Port
CS5530
(CRT/LCD TFT)
PCI Bus
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
www.national.com







30151-33 pdf, 数据表
1.0 Architecture Overview
The National Semiconductor Geode GXm processor is
an x86-compatible 32-bit microprocessor. The decoupled
load/store unit (within the memory management unit)
allows multiple instructions in a single clock cycle. Other
features include single-cycle execution, single-cycle
instruction decode, 16 KB write-back cache, and clock
rates up to 266 MHz. These features are made possible
by the use of advanced-process technologies and super-
pipelining.
The GXm processor has low power consumption at all
clock frequencies. Where additional power savings are
required, designers can make use of Suspend mode, Stop
Clock capability, and System Management Mode (SMM).
The GXm processor is divided into major functional blocks
(as shown in Figure 1-1):
• Integer Unit
• Floating Point Unit (FPU)
• Write-Back Cache Unit
• Memory Management Unit (MMU)
• Internal Bus Interface Unit
• Integrated Functions
Instructions are executed in the integer unit and in the
floating point unit. The cache unit stores the most recently
used data and instructions and provides fast access to
this information for the integer and floating point units.
1.1 INTEGER UNIT
The integer unit consists of:
• Instruction Buffer
• Instruction Fetch
• Instruction Decoder and Execution
The superpipelined integer unit fetches, decodes, and
executes x86 instructions through the use of a six-stage
integer pipeline.
The instruction fetch pipeline stage generates, from the
on-chip cache, a continuous high-speed instruction
stream for use by the processor. Up to 128 bits of code
are read during a single clock cycle.
Branch prediction logic within the prefetch unit generates
a predicted target address for unconditional or conditional
branch instructions. When a branch instruction is
detected, the instruction fetch stage starts loading instruc-
tions at the predicted address within a single clock cycle.
Up to 48 bytes of code are queued prior to the instruction
decode stage.
The instruction decode stage evaluates the code stream
provided by the instruction fetch stage and determines the
number of bytes in each instruction and the instruction
type. Instructions are processed and decoded at a maxi-
mum rate of one instruction per clock.
The address calculation function is super-pipelined and
contains two stages, AC1 and AC2. If the instruction
refers to a memory operand, AC1 calculates a linear
memory address for the instruction.
The AC2 stage performs any required memory manage-
ment functions, cache accesses, and register file
accesses. If a floating point instruction is detected by
AC2, the instruction is sent to the floating point unit for
processing.
The execution stage, under control of microcode, exe-
cutes instructions using the operands provided by the
address calculation stage.
Write-back, the last stage of the integer unit, updates the
register file within the integer unit or writes to the
load/store unit within the memory management unit.
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
Internal Bus Interface Unit
X-Bus
FPU
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
www.national.com
SDRAM Port
CS5530
(CRT/LCD TFT)
Figure 1-1. Internal Block Diagram
8
PCI Bus
Revision 3.1







30151-33 equivalent, schematic
Signal Definitions (Continued)
Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number (Continued)
Pin
No. Signal Name
AB1 DCLK
AB2 PIXEL17
AB3 VID_DATA6
AB4 VID_DATA7
AB23 MA4
AB24 MA5
AB25 MA6
AB26 MA7
AC1 PCLK
AC2 FLT#
AC3 VID_DATA4
AC4 VSS
AC5 VOLDET
AC6 VSS
AC7 VCC2
AC8 VSS
AC9 VSS
AC10 VCC3
AC11 VSS
AC12 VSS
AC13 VSS
AC14 VSS
AC15 VSS
Pin
No. Signal Name
AC16 VSS
AC17 VCC2
AC18 VSS
AC19 VSS
AC20 VCC3
AC21 VSS
AC22 DQM6
AC23 VSS
AC24 MA8
AC25 MA9
AC26 MA10
AD1 VID_RDY
AD2 VID_DATA5
AD3 VID_DATA3
AD4 VID_DATA0
AD5 ENA_DISP
AD6 MD63
AD7 VCC2
AD8 MD62
AD9 MD29
AD10 VCC3
AD11 MD59
AD12 MD26
Pin
No. Signal Name
AD13 MD56
AD14 MD55
AD15 MD22
AD16 CKEB
AD17 VCC2
AD18 MD51
AD19 MD18
AD20 VCC3
AD21 MD48
AD22 DQM3
AD23 CS1#
AD24 MA11
AD25 BA0
AD26 BA1
AE1 VSS
AE2 VSS
AE3 VID_DATA2
AE4 SDCLK3
AE5 SDCLK1
AE6 RW_CLK
AE7 VCC2
AE8 SDCLK_IN
AE9 MD61
Pin
No. Signal Name
AE10 VCC3
AE11 MD28
AE12 MD58
AE13 MD25
AE14 MD24
AE15 MD54
AE16 MD21
AE17 VCC2
AE18 MD20
AE19 MD50
AE20 VCC3
AE21 MD17
AE22 DQM7
AE23 CS3#
AE24 MA12
AE25 VSS
AE26 VSS
AF1 VSS
AF2 VSS
AF3 VID_DATA1
AF4 SDCLK0
AF5 SDCLK2
AF6 MD31
Pin
No. Signal Name
AF7 VCC2
AF8 SDCLK_OUT
AF9 MD30
AF10 VCC3
AF11 MD60
AF12 MD27
AF13 MD57
AF14 VSS
AF15 MD23
AF16 MD53
AF17 VCC2
AF18 MD52
AF19 MD19
AF20 VCC3
AF21 MD49
AF22 MD16
AF23 DQM2
AF24 CKEA
AF25 VSS
AF26 VSS
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16
Revision 3.1










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