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DAC7641 数据手册 PDF ( 16-Bit/ Voltage Output DIGITAL-TO-ANALOG CONVERTER )

零件编号 DAC7641
描述 16-Bit/ Voltage Output DIGITAL-TO-ANALOG CONVERTER
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 

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DAC7641 数据手册, 描述, 功能
®
DAC7641 ®
DAC7641
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q LOW POWER: 2.5mW
q UNIPOLAR OR BIPOLAR OPERATION
q SETTLING TIME: 10µs to 0.003%
q 15-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
q PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
q DATA READBACK
q DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
q PROCESS CONTROL
q ATE PIN ELECTRONICS
q CLOSED-LOOP SERVO-CONTROL
q MOTOR CONTROL
q DATA ACQUISITION SYSTEMS
q DAC-PER-PIN PROGRAMMERS
DESCRIPTION
The DAC7641 is a 16-bit, voltage output digital-to-
analog converter (DAC) with guaranteed 15-bit mono-
tonic performance over the specified temperature range.
It accepts 16-bit parallel input data, has double-buffered
DAC input logic (allowing asynchronous update), and
provides a readback mode of the internal input registers.
Programmable asynchronous reset clears all registers to
a mid-scale code of 8000H or to a zero-scale of 0000H.
The DAC7641 can operate from a single +5V supply or
from +5V and –5V supplies.
Low power and small size per DAC make the DAC7641
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-
loop servo-control. The DAC7641 is available in a
TQFP-32 package, and offers guaranteed specifica-
tions over the –40°C to +85°C temperature range.
VDD VSS VCC
VREFL
Sense
VREFL
VREFH
VREFH
Sense
DATA I/O
16 I/O
Buffer
CS Control
R/W Logic
Input
Register
DAC
Register
AGND DGND RST RSTSEL LDAC
DAC
VOUT
VOUT Sense
DAC7641
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 2000 Burr-Brown Corporation
PDS-11532A
DAPrCint7ed6in4U1.S.A. June, 2000
®




DAC7641 pdf, 数据表
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
+5V
LDAC
0
BROADBAND NOISE
8000H to 7FFFH
Time (1µs/div)
Time (10ms/div)
BW = 10kHz
Code = 8000H
1000
OUTPUT NOISE VOLTAGE vs FREQUENCY
100
10
10
100
1000
10000 100000 1000000
Frequency (Hz)
12
10
8
6
4
2
0
0
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DATA BITS
1234
Logic Input Level for Data Bits (V)
5
5
4
3
2
1
0
0.01
OUTPUT VOLTAGE vs RLOAD
Source
Sink
0.1 1 10
RLOAD (k)
100
®
DAC7641
8


DAC7641 equivalent, schematic
+V
+2.5V
24 VSS
VOUT Sense 23
VOUT 22
DAC7641
VOUT
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H
2000H
4000H 6000H
8000H
A000H C000H
E000H FFFFH
Digital Input Code
FIGURE 12. Low Cost Single-Supply Configuration.
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7641. Note
that the internal register is edge triggered and not level
triggered. When the LDAC signal is transitioned to HIGH,
the digital word currently in the register is latched.
The double-buffered architecture is designed so that the
DAC input register can be written to at any time.
R/W CS RST RSTSEL LDAC REGISTER REGISTER
INPUT
MODE
LLH
HLH
XHH
XHH
XX
XX
X
X
X
X
L
H
X Write
Hold
Write Input
X Read
Hold
Read Input
Hold
Write
Update
H Hold
Hold
Hold
X Reset to Zero Reset to Zero
X Reset to Midscale Reset to Midscale
TABLE I. DAC7641 Logic Truth Table.
DIGITAL TIMING
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7641.
DIGITAL INPUT CODING
The DAC7641 input data is in Straight Binary format. The
output voltage is given by Equation 1.
( )VOUT = VREFL +
VREFH – VREFL
65, 536
•N
(1)
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
®
DAC7641
16



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