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PDF ( 数据手册 , 数据表 ) DAC7631EB1K

零件编号 DAC7631EB1K
描述 Serial Input/ 16-Bit/ Voltage Output DIGITAL-TO-ANALOG CONVERTER
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 


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DAC7631EB1K 数据手册, 描述, 功能
®
DAC7631 ®
DAC7631
For most current data sheet and other product
information, visit www.burr-brown.com
Serial Input, 16-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q LOW POWER: 2.5mW
q UNIPOLAR OR BIPOLAR OPERATION
q SETTLING TIME: 10µs to 0.003%
q 15-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
q USER SELECTABLE RESET TO
MID-SCALE OR ZERO-SCALE
q SMALL SSOP-20 PACKAGE
DESCRIPTION
The DAC7631 is a serial input, 16-bit, voltage out-
put Digital-to-Analog Converter (D/A) with guaran-
teed 15-bit monotonic performance over the –40°C to
+85°C temperature range. An asynchronous reset clears
all registers to either mid-scale (8000H) or zero-scale
(0000H), selectable via the RESETSEL pin. The de-
vice can be powered from a single +5V supply or from
dual +5V and –5V supplies.
APPLICATIONS
q ATE PIN ELECTRONICS
q PROCESS CONTROL
q CLOSED-LOOP SERVO-CONTROL
q MOTOR CONTROL
q DATA ACQUISITION SYSTEMS
Low power and small size makes the DAC7631 ideal
for process control, data acquisition systems, and
closed-loop servo-control. The device is available in a
SSOP-20 package, and is guaranteed over the
–40°C to +85°C temperature range.
SDO
VDD
VCC
VSS
VREFL
Sense
VREFL
VREFH
VREFH
Sense
CLK
CS
Shift
Register
SDI
DAC7631
Input
Register
DAC
Register
LOAD
RSTSEL RST
LDAC
DAC A
DGND
VOUT
VOUT Sense
AGND
SBAS122
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-11536A
DPArintCed7in6U3.S.1A. August, 2000
®







DAC7631EB1K pdf, 数据表
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
+5V
LDAC
0
BROADBAND NOISE
8000H to 7FFFH
Time (1µs/div)
BW = 10kHz
Code = 8000H
Time (10ms/div)
1000
OUTPUT NOISE VOLTAGE vs FREQUENCY
100
10
10
100
1000
10000 100000 1000000
Frequency (Hz)
5
4
3
2
1
0
0.01
OUTPUT VOLTAGE vs RLOAD
Source
Sink
0.1 1 10
RLOAD (k)
100
®
DAC7631
8







DAC7631EB1K equivalent, schematic
SCK
DIN
CS
DAC7631
CLK
SDI SDO
CS
DAC7631
CLK
SDI SDO
CS
DAC7631
CLK
SDI SDO
CS
To
Other
Serial
Devices
FIGURE 14. Daisy-chaining DAC7631.
DAC updates; i.e., the LDAC pin can be driven with a
separate signal, such as a timing clock, which need not be
directly related to the serial data timing. This makes it easy
to synchronize DAC7631 updates with external events or
with other DACs.
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is LOW when CS rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both CS and CLK are used, CS should rise only when CLK
is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table II for more information.
CS(1)
CLK(1)
LOAD
RST SERIAL SHIFT REGISTER
H(2)
X(3)
H
H
L(4) L H H
L (5) H
H
LHH
H(6) X L(7) H
H(6) X
H (8)
No Change
No Change
Advanced One Bit
Advanced One Bit
No Change
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOAD is LOW, the DAC register will
change. This will corrupt the data in each DAC register that has been
erroneously selected. (8) Rising edge of RST causes no change in the
contents of the serial shift register.
TABLE II. Serial Shift Register Truth Table.
SERIAL-DATA OUTPUT
The Serial-Data Output (SDO) is the internal shift register’s
output. For DAC7631, the SDO is a driven output and does
not require an external pull-up. Any number of DAC7631’s
can be daisy chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain,
as shown in Figure 14.
DIGITAL TIMING
Figure 15 and Table III provide detailed timing for the
digital interface of the DAC7631.
DIGITAL INPUT CODING
The DAC7631 input data is in Straight Binary format. The
output voltage is given by Equation 1:
( )VOUT = VREFL +
VREFH – VREFL
65, 536
•N
(1)
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
The DAC7631 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7631 offers
both a differential reference input, as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows a transistor
to be placed within the loop to implement a digitally-
programmable, unidirectional current source. The availabil-
ity of a differential reference allows programmability for
both the full-scale and zero-scale currents. The output cur-
rent is calculated as:
I OUT
=

 
VREFH – VREF
R SENSE
L


N
65, 536

( )+ VREFL / RSENSE
(2)
®
DAC7631
16










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