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PDF ( 数据手册 , 数据表 ) DAC709KH

零件编号 DAC709KH
描述 Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 


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DAC709KH 数据手册, 描述, 功能
DAC707
® DAC708
DAC709
Microprocessor-Compatible
16-BIT DIGITAL-TO-ANALOG CONVERTERS
FEATURES
q TWO-CHIP CONSTRUCTION
q HIGH-SPEED 16-BIT PARALLEL, 8-BIT
(BYTE) PARALLEL, AND SERIAL INPUT
MODES
q DOUBLE-BUFFERED INPUT REGISTER
CONFIGURATION
q VOUT AND IOUT MODELS
DESCRIPTION
The DAC708 and DAC709 are 16-bit converters de-
signed to interface to an 8-bit microprocessor bus. 16-
bit data is loaded in two successive 8-bit bytes into
parallel 8-bit latches before being transferred into the
D/A latch. The DAC708 and DAC709 are current and
voltage output models respectively and are in 24-pin
hermetic DIPs. Input coding is Binary Two’s Comple-
ment (bipolar) or Unipolar Straight Binary (unipolar,
when an external logic inverter is used to invert the
MSB). In addition, the DAC708/709 can be loaded
serially (MSB first).
The DAC707 is designed to interface to a 16-bit bus.
q HIGH ACCURACY:
Linearity Error ±0.003% of FSR max
Differential Linearity Error ±0.006% of FSR
max
q MONOTONIC (TO 14 BITS) OVER
SPECIFIED TEMPERATURE RANGE
q HERMETICALLY SEALED
q LOW COST PLASTIC VERSIONS
AVAILABLE (DAC707JP/KP)
Data is written into a 16-bit latch and subsequently the
D/A latch. The DAC707 has bipolar voltage output
and input coding is Binary Two’s Complement (BTC).
All models have Write and Clear control lines as well
as input latch enable lines. In addition, DAC708 and
DAC709 have Chip Select control lines. In the bipolar
mode, the Clear input sets the D/A latch to give zero
voltage or current output. They are all 14-bit accurate
and are complete with reference, and for the DAC707,
and DAC709, a voltage output amplifier. All models
are available with an optional burn-in screening.
8-Bit
(DAC708, 709)
or
16-Bit (DAC707)
Serial
(DAC708, 709)
Serial
Data
High
Byte
Latch
Low
Byte
Latch
D/A
Latch
16-Bit
D/A
Con-
verter
Reference
Circuit
Bipolar
Offset
Summing Junction (708, 709)
10V Range (708, 709)
VOUT
Latch Enables/
Mode Select
CLEAR
WRITE
CHIP SELECT
Control
Logic
DAC707 or DAC709
Only
DAC707/708/709 Block Diagram
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
PDS-557H







DAC709KH pdf, 数据表
VOLTAGE OUTPUT MODELS
Digital
Input
Code
Analog Output
Unipolar, 0 to +10V(1)
16-Bit
15-Bit
14-Bit
Units
Digital
Input
Code
Analog Output
Bipolar, ±10V
Bipolar, ±5V
16-Bit
15-Bit
14-Bit
16-Bit
15-Bit
14-Bit
Units
One LSB
FFFFH
0000H
153
+9.99985
0
305
+9.99969
0
610
+9.99939
0
µV One LSB
305
610 1224 153
305
610
V 7FFFH +9.99960 +9.99939 +9.99878 +4.99980 +4.99970 +4.99939
V 8000H –10.0000 –10.0000 –10.0000 –5.0000 –5.0000 –5.0000
CURRENT OUTPUT MODELS
µV
V
V
Digital
Input
Code
Analog Output
Unipolar, 0 to –2mA(1)
16-Bit
15-Bit
14-Bit
Units
Digital
Input
Code
16-Bit
Analog Output
Bipolar, ±1mA
15-Bit
14-Bit
Units
One LSB
FFFFH
0000H
0.031
–1.99997
0
0.061
–1.99994
0
0.122
–1.99988
0
µA
mA
mA
One LSB
7FFFH
8000H
0.031
–0.99997
+1.00000
0.061
–0.99994
+1.00000
0.122
–0.99988
+1.00000
µA
mA
mA
NOTE: (1) MSB assumed to be inverted externally.
TABLE II. Digital Input and Analog Output Voltage/Current Relationships.
INTERFACE LOGIC AND TIMING
DAC708/709
The signals CHIP SELECT (CS), WRITE (WR), register
enables (A0, A1, and A2) and CLEAR (CLR), provide the
control functions for the microprocessor interface. They are
all active in the “low” or logic “0” state. CS must be low to
access any of the registers. A0 and A1 steer the input 8-bit
data byte to the low- or high-byte input latch respectively. A2
gates the contents of the two input latches through to the D/A
latch in parallel. The contents are then applied to the input of
the D/A converter. When WR goes low, data is strobed into
the latch or latches which have been enabled.
The serial input mode is activated when both A0 and A1 are
logic “0” simultaneously. The D0 (D8)/SI input data line
accepts the serial data MSB first. Each bit is clocked in by
a WR pulse. Data is strobed through to the D/A latch by A2
going to logic “0” the same as in the parallel input mode.
Each of the latches can be made “transparent” by maintain-
ing its enable signal at logic “0”. However, as stated above,
when both A and A are logic “0” at the same time, the
01
serial mode is selected.
The CLR line resets both input latches to all zeros and sets
the D/A latch to 0000H. This is the binary code that gives a
null, or zero, at the output of the D/A in the bipolar mode.
In the unipolar mode, activating CLR will cause the output
to go to one-half of full scale.
The maximum clock rate of the latches is 10MHz. The
minimum time between write (WR) pulses for successive
enables is 20ns. In the serial input mode (DAC708 and
DAC709), the maximum rate at which data can be clocked
into the input shift register is 10MHz.
The timing of the control signals is given in Figure 6.
DAC707
The DAC707 interface timing is the same as that described
above except instead of two 8-bit separately-enabled input
latches, it has a single 16-bit input latch enabled by A0. The
LOGIC TIMING - Parallel or Serial Data Input Over Temperature
ns, min ns, max
TDW Data valid to end of WR
TCW CS valid to end of WR
TAW A0, A1, A2 valid to end of WR
TWP Write pulse width
TDH Data hold after end of WR
80
80
80
80
0
TIMING DIAGRAM
tCW
CS
A0, A1, A2
tAW
D0-D15, SI
tDW
tDH
WR
tWP
FIGURE 6. Logic Timing Diagram.
D/A latch is enabled by A . Also, there is no serial-input
1
mode and no CHIP SELECT (CS) line.
INSTALLATION
CONSIDERATIONS
Due to the extremely-high accuracy of the D/A converter,
system design problems such as grounding and contact
resistance become very important. For a 16-bit converter
with a +10V full-scale range, 1LSB is 153µV. With a load
current of 5mA, series wiring and connector resistance of
only 30mwill cause the output to be in error by 1LSB. To
understand what this means in terms of a system layout, the
resistance of typical 1 ounce copper-clad printed circuit
board material is approximately 1/2mper square. In the
example above, a 10 milliinch-wide conductor 60 milliinches
long would cause a 1LSB error.
®
DAC707/708/709
8














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