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PDF ( 数据手册 , 数据表 ) DAC3550A

零件编号 DAC3550A
描述 DAC 3550A STEREO AUDIO DAC
制造商 ETC
LOGO ETC LOGO 


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DAC3550A 数据手册, 描述, 功能
MICRONAS
DAC 3550A
Stereo Audio DAC
Edition July 23, 1999
6251-140697-41EDS
MICRONAS







DAC3550A pdf, 数据表
DAC 3550A
2.10. Clock System
The advantage of the DAC 3550A clock system is that
no external master clock is needed. Most DACs need
256 × fsaudio, 384 × fsaudio, or at least an asynchro-
nous clock.
All internal clocks are generated by a PLL circuit,
which locks to the I2S bit clock (CLI). If no I2S clock is
present, the PLL runs free, and it is guaranteed that
there is always a clock to keep the IC controllable by
I2C.
The device can be set to two different modes:
Standard mode
MPEG mode
In the standard mode, I2C subaddressing is possible
(ADR0, ADR1, ADR2).
MPEG mode always uses ADR3.
To select the modes, the MCS1/MCS2 pins must be
set according to Table 22.
Table 22: Operation Modes
MCS1 MCS2 Mode
Sub-
address
0
0
Stan-
ADR0
dard
0
1
Stan-
ADR1
dard
1
0
Stan-
ADR2
dard
1 1 MPEG ADR3
Default
Sample
Rate
3248 kHz
3248 kHz
3248 kHz
Automatic
2.10.1. Standard Mode
without I2C
In standard mode, sample rates from 48 kHz to
32 kHz are handled without I2C control automati-
cally. The setting for this range is the default setting.
with I2C
Sample rates below 32 kHz require an I2C control to
set the PLL divider. This ensures that even at low
sample rates, the DAC 3550A runs at a high clock
rate. This avoids audible effects due to the noise-
shaping technique of the DAC 3550A. Sample rate
range is continuous from 8 to 50 kHz. The I2C set-
ting of low sample rates must follow according to
Section 3.6. Control Registerson page 15.
An additional mode allows automatic sample rate
detection. In this case, the clock oscillator is
required and must run at frequencies between
13.3 MHz to 17 MHz. This mode, however, does not
support continuous sample rates. Only the following
sample rates are allowed:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
The sample rate detection allows a tolerance of
±200 ppm at WSI.
If the oscillator is not used for automatic sample rate
detection, it can be used as a general-purpose clock
for the application. The frequency range in this case is
10 MHz to 25 MHz.
2.10.2. MPEG Mode
This mode should be used in conjunction with
MAS 3507D in MPEG player applications. In this case
a 14.725 MHz signal is needed to provide a clock for
the MAS 3507D and to allow an automatic sample rate
detection in the DAC 3550A. All MPEG sample rates
from 8 to 48 kHz can be detected. The internal pro-
cessing and the DAC itself are automatically adjusted
to keep constant performance throughout the entire
range. I2C control for sample rate adjustment is not
needed in this case. Register SR_REG[0:2] is locked
to SRC_A; see Section 3.6. Control Registerson
page 15.
The MPEG sample rates:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
As in standard mode, the sample rate detection allows
a tolerance of ±200 ppm at WSI.
Subaddressing is not possible in MPEG mode; this
means, in multi-DAC systems, only one DAC 3550A
can run in MPEG mode.
8 Micronas







DAC3550A equivalent, schematic
DAC 3550A
I2C Sub-
address
(hex)
Number
of Bits
Mode
Global Configuration GCFG
03 8
w
Function
global configuration
bit[7] not used, set to 0
bit[6]
select 3V-5 V mode
0 3V
1 5V
bit[5]
power-mode
0 normal
1 low power
bit[4]
AUX2 select
0 AUX2 off
1 AUX2 on
bit[3]
AUX1 select
0 AUX1 off
1 AUX1 on
bit[2]
DAC select
0 DAC off
1 DAC on (default)
bit[1]
aux-mono/stereo
0 stereo
1 mono
bit[0]
invert right power amplifier
0 not inverted
1 inverted
Default
Values
(hex)
Name
4H
SEL_53V
PWMD
INSEL_AUX2
INSEL_AUX1
INSEL_DAC
AUX_MS
IRPA
16 Micronas










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