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PDF ( 数据手册 , 数据表 ) DAC2815AP

零件编号 DAC2815AP
描述 DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER 8-Bit Port Interface
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 


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DAC2815AP 数据手册, 描述, 功能
® DAC2815
DUAL 12-BIT DIGITAL-TO-ANALOG
CONVERTER (8-Bit Port Interface)
FEATURES
q COMPLETE DUAL DAC —
INCLUDES INTERNAL REFERENCES AND
OUTPUT AMPLIFIERS
q GUARANTEED SPECIFICATIONS OVER
TEMPERATURE
q GUARANTEED MONOTONIC OVER
TEMPERATURE
q HIGH-SPEED 8 + 4-BIT PARALLEL
INTERFACE
q LOW POWER: 300mW (150mW/DAC)
q LOW GAIN DRIFT: 5ppm/°C
q LOW NONLINEARITY: ±1/2 LSB max
q UNIPOLAR OR BIPOLAR OUTPUT
q CLEAR/RESET TO UNIPOLAR OR
BIPOLAR ZERO
DESCRIPTION
The DAC2815 is one in a family of dual and quad 12-
bit digital-to-analog converters (DACs). Serial, 8-bit,
12-bit interfaces are available.
The DAC2815 is complete. It contains CMOS logic,
switches, a high-performance buried-zener reference,
and low-noise bipolar output amplifiers. No external
components are required for either unipolar 0 to 10V,
0 to –10V, or bipolar ±10V output ranges.
The DAC2815 has a 2-byte (8 + 4) double-buffered
interface. Data is first loaded (level transferred) into
the input registers in two steps for each DAC. Then
both DACs are updated simultaneously. The DAC has
an asynchronous clear control for reset to unipolar or
bipolar zero depending on the mode selected. This
feature is useful for power-on reset or system calibra-
tion. The DAC2815 is packaged in a 28-pin plastic
DIP rated for the –40°C to +85°C extended industrial
temperature range.
High-stability laser-trimmed thin film resistors assure
high reliability and true 12-bit integral and differential
linearity over the full specified temperature range.
+VL 10
+VS 12
–VS 8
AGND 11
DGND 28
8-Bit
Port and
Control In
Logic
DAC2815
10V
Ref
10k
10k
A3
DAC A
DAC B
20k
20k
A1
20k
20k
A2
17 +VREF Out
18 Inv In
14 Inv Out
13 VREF In
20 BPO A
16 VOUT A
19 BPO B
15 VOUT B
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1991 Burr-Brown Corporation
PDS-1110B
Printed in U.S.A. October, 1993







DAC2815AP pdf, 数据表
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC2815 are TTL and 5V CMOS
compatible. Input codes for the DAC2815 are either USB
(Unipolar Straight Binary) or BOB (Bipolar Offset Binary)
depending on the mode of operation. See Figure 3 for ±10V
bipolar connection. See Figures 4 and 5 for 0 to 10V and 0
to –10V unipolar connections.
UNIPOLAR AND BIPOLAR
OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
UNIPOLAR (USB)
FFFHEX
800HEX
7FF
HEX
000HEX
+Full scale
+1/2 Full scale
+1/2 Full scale – 1 LSB
Zero
BIPOLAR (BOB)
+Full scale
Zero
Zero – 1 LSB
–Full scale
INTEGRAL OR RELATIVE LINEARITY
This term, also known as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of ±1 LSB maximum guarantees monotonicity.
UNIPOLAR OFFSET ERROR
The output voltage for code 000HEX when the DAC is in the
unipolar mode of operation.
BIPOLAR ZERO ERROR
The output voltage for code 800 when the DAC is in the
HEX
bipolar mode of operation.
GAIN ERROR
The deviation of the output voltage span (VMAX – VMIN) from
the ideal span of 10V – 1 LSB (unipolar mode) or 20V – 1
LSB (bipolar mode). The gain error is specified with and
without the internal +10V reference error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to ±0.012% (1/2 LSB) is specified for the DAC2815.
DIGITAL-TO-ANALOG GLITCH
Ideally, the DAC output would make a clean step change in
response to an input code change. In reality, glitches occur
during the transition. See Typical Performance Curves.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC—see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nV–s. See table of electrical specifications.
DIGITAL FEEDTHROUGH
Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs—see Typical Performance
Curves.
OPERATION
Depending on the address selected, the 4 MSBs or the 8
LSBs are written into the appropriate input register for each
DAC when the WR signal is brought low. This data is
latched in the input register when the WR goes high. Data
are then transferred from the input registers to the DAC latch
registers by bring LE low. The data are latched in the DAC
latch registers when LE goes high. Both DACs are updated
simultaneously.
When CLR is brought low, the input registers are cleared to
000HEX (–10V), while the DAC registers = 800HEX. If LE is
brought low, the DACs are updated with 000 resulting in
HEX
–10V (bipolar) or 0V (unipolar) on the output.
CIRCUIT DESCRIPTION
Each of the two DACs in the DAC2815 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a reference inverter
(for a –10.0V reference) are shared by both DACs.
Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at V .
REF
Current from the ladder is switched either to IOUT or AGND
by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
VREF
R
2R
R
2R
R
2R
2R 2R R
RFB
IOUT
D11
(MSB)
D10
D9
D0
(LSB)
AGND
FIGURE 1. Simplified Circuit Diagram of DAC Cell.
®
DAC2 815
8














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