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PDF ( 数据手册 , 数据表 ) DAC2814AP

零件编号 DAC2814AP
描述 DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER Serial Interface
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 


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DAC2814AP 数据手册, 描述, 功能
® DAC2814
DUAL 12-BIT DIGITAL-TO-ANALOG
CONVERTER (Serial Interface)
FEATURES
q COMPLETE DUAL DAC —
INCLUDES INTERNAL REFERENCES AND
OUTPUT AMPLIFIERS
q GUARANTEED SPECIFICATIONS OVER
TEMPERATURE
q GUARANTEED MONOTONIC OVER
TEMPERATURE
q HIGH-SPEED SERIAL INTERFACE
(10MHz CLOCK)
q LOW POWER: 300mW (150mW/DAC)
q LOW GAIN DRIFT: 5ppm/°C
q LOW NONLINEARITY: ±1/2 LSB max
q UNIPOLAR OR BIPOLAR OUTPUT
q CLEAR/RESET TO UNIPOLAR OR
BIPOLAR ZERO
DESCRIPTION
The DAC2814 is one in a family of dual and quad 12-
bit digital-to-analog converters. Serial, 8-bit, 12-bit
interfaces are available.
The DAC2814 is complete. It contains CMOS logic,
switches, a high-performance buried-zener reference,
and low-noise bipolar output amplifiers. No external
components are required for either unipolar 0 to 10V,
0 to –10V, or bipolar ±10V output ranges.
The DAC2814 has a high-speed serial interface
capable of being clocked at 10MHz. Serial data are
clocked DAC B MSB first into a 24-bit shift register,
then strobed into each DAC separately or simulta-
neously as required. The DAC has an asynchronous
clear control for reset to unipolar or bipolar zero
depending on the mode selected. This feature is useful
for power-on reset or system calibration. The DAC2814
is packaged in a 24-pin plastic DIP rated for the –40°C
to +85°C extended industrial temperature range.
High-stability laser-trimmed thin film resistors assure
high reliability and true 12-bit integral and differential
linearity over the full specified temperature range.
+VL 6
+VS 10
–VS 7
AGND 8
DGND 1
Serial
Data and
Control In
Logic
Serial
Data 5
Out
DAC2814
10V
Ref
10k
10k
A3
DAC A
DAC B
20k
20k
A1
20k
20k
A2
16 +VREF Out
15 Inv In
12 Inv Out
11 VREF In
19 BPO A
14 VOUT A
18 BPO B
17 VOUT B
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1991 Burr-Brown Corporation
PDS-1103B
Printed in U.S.A. October, 1993







DAC2814AP pdf, 数据表
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC2814 are TTL and 5V CMOS
compatible. Input codes for the DAC2814 are either USB
(Unipolar Straight Binary) or BOB (Bipolar Offset Binary)
depending on the mode of operation. See Figure 3 for ±10V
bipolar connection. See Figures 4 and 5 for 0 to 10V and 0
to –10V unipolar connections.
UNIPOLAR AND BIPOLAR
OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
UNIPOLAR (USB)
FFFHEX
800HEX
7FFHEX
000HEX
+Full scale
+1/2 Full scale
+1/2 Full scale – 1 LSB
Zero
BIPOLAR (BOB)
+Full scale
Zero
Zero – 1 LSB
–Full scale
INTEGRAL OR RELATIVE LINEARITY
This term, also know as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of ±1 LSB maximum guarantees monotonicity.
UNIPOLAR OFFSET ERROR
The output voltage for code 000HEX when the DAC is in
unipolar mode of operation.
BIPOLAR ZERO ERROR
The output voltage for code 800HEX when the DAC is in the
bipolar mode of operation.
GAIN ERROR
The deviation of the output voltage span (VMAX – VMIN)
from the ideal span of 10V – 1 LSB (unipolar mode) or 20V
– 1 LSB (bipolar mode). The gain error is specified with and
without the internal +10V reference error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to ±0.012% (1/2 LSB) is specified for the DAC2814.
DIGITAL-TO-ANALOG GLITCH
Ideally, the DAC output would make a clean step change in
response to an input code change. In reality glitches occur
during the transition. See Typical Performance Curves.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC—see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nV–s. See table of electrical specifications.
DIGITAL FEEDTHROUGH
Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs—see Typical Performance
Curves.
OPERATION
DACs can be updated simultaneously or independently as
required. Data are transferred on falling clock edges into a
24-bit shift register. DAC B MSB is loaded first. Data are
transferred to the DAC registers when the LATCH signals
are brought low. The data are latched when the LATCH
signals are brought high. Both LATCH signals may be tied
together to allow simultaneous update of the DACs if re-
quired. The output of the DAC shift register is provided to
allow cascading of several DACS on the same bit stream.
By using separate signals for LATCH A and LATCH B, it
is possible to update either one of the two DACs every 12
clock cycles.
When CLR is brought low, the input shift registers are
cleared to 000HEX, while the DAC registers = 800HEX. If
LATCH is brought low after CLR, the DACs are updated
with 000HEX resulting in –10V (Bipolar) or 0V (Unipolar) on
the output.
CIRCUIT DESCRIPTION
Each of the two DACs in the DAC2814 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a reference inverter
(for a –10.0V reference) are shared by both DACs.
Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at VREF.
Current from the ladder is switched either to IOUT or AGND
by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
digital input code. This makes the resistance at VREF con-
stant (it can be driven by either a voltage or current refer-
ence). The reference can be either positive or negative
polarity with a range of up to ±10V.
VREF
R
2R
R
2R
R
2R
2R 2R R
RFB
IOUT
D11
(MSB)
D10
D9
D0
(LSB)
AGND
FIGURE 1. Simplified Circuit Diagram of DAC Cell.
®
DAC 2 814
8














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