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PDF ( 数据手册 , 数据表 ) DAC14135MTX

零件编号 DAC14135MTX
描述 14-bit/ 135MSPS D/A Converter
制造商 National Semiconductor
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DAC14135MTX 数据手册, 描述, 功能
N
DAC14135
14-bit, 135MSPS D/A Converter
November 1999
General Description
The DAC14135 is a monolithic 14-bit, 135MSPS digital-to-analog
converter. The device has been optimized for use in cellular base
stations and other applications where high resolution, high
sampling rate, wide dynamic range, and compact size are
required. The DAC14135 has many integrated features including
a proprietary segmented DAC core, differential current outputs, a
band-gap voltage reference, and TTL/CMOS compatible inputs.
The converter features an 85dBc spurious free dynamic range
(SFDR) at low frequencies and a 70dBc SFDR with 20MHz
output signals. The 48-pin TSSOP package provides an extremely
small footprint for applications where space is a critical consider-
ation. The DAC14135 operates from a single +5V power supply.
The digital power supply can also operate from +3.3V for lower
power consumption and compatibility with +3.3V data inputs. The
DAC14135 is fabricated in a 0.5µm CMOS process and is speci-
fied over the industrial temperature range of -40°C to +85°C.
National Semiconductor thoroughly tests each part to verify full
compliance with the guaranteed specifications.
Features
• 135 MSPS
• Wide dynamic range
SFDR @ 1MHz fout: 85dBc
SFDR @ 5MHz fout: 79dBc
SFDR @ 20MHz fout: 70dBc
• Differential Current Outputs
• Low power consumption: 185mW
• Very small package: 48-pin TSSOP
• TTL/CMOS (+3.3V or +5V) inputs
Applications
• Cellular Basestations:
GSM, WCDMA, DAMPS, etc.
• Multi-carrier Basestations
• Multi-standard Basestations
• Direct digital synthesis (DDS)
• ADSL modems
• HFC modems
W-CDMA ACPR
-30
-40
-50 ACPR Lower
72.1dB
-60
Fs = 32.768MSPS
ACPR Upper
73dB
-70
-80
-90
-100
-110
-120
2 4 6 8 10 12 14 16
Frequency (MHz)
Four-Tone SFDR
0
SFDR > 70dBc
-20
-40
Fs = 135MSPS
Fout1 = 6.2MHz
Fout2 = 9.31MHz
Fout3 = 18.8MHz
Fout4 = 21.95MHz
Ampl. = 0dBFS
-60
-80
-100
5 10 15 20 25 30
Frequency (MHz)
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com







DAC14135MTX pdf, 数据表
ridden by an external bandgap reference voltage. The
reference ground (REFLO) should always be tied to
analog ground. The REFIO pin should be bypassed to
REFLO using a 0.1µF capacitor. For reduced noise, an
external compensation capacitor (0.1µF) should also be
used to bypass the internal reference loop from pin
REFCOMP to AGND. Figure 3 shows the internal
voltage reference loop functional schematic.
REFCOMP
0.1µF
REFIO
0.1µF
FSADJ
Iref
Rset
DAC14135
Band-
gap
1.235V
PMOS
mirrors
REFLO
Analog Outputs
The differential analog outputs, IOUTT and IOUTF, are high
impedance current source outputs. These outputs, if
terminated into 50at 20mA full scale current, will
generate a differential voltage output at 2Vpp. The output
compliance of each of the current outputs of the
DAC14135 is -0.5V to +1.25V. The differential outputs
can be converted to a single-ended output using an RF
center-tapped transformer or a differential to single-
ended amplifier. The IOUTT and IOUTF traces on the
printed circuit board should be short and matched with
adequate analog grounding nearby. One example of an
AC coupled differential to single-ended topology is shown
in Figure 4.
DAC14135
IOUTT
IOUTF
50
100
T1-1T
Figure 3: Internal Voltage Loop
Functional Schematic
50
A reference current source (Iref) from pin FSADJ to
ground may be used to set the full scale output current
(Ifs) of the DAC14135. The full scale current is given by,
Ifs = 42.67 x Iref
Alternatively, a resistor (Rset) from FSADJ to AGND may
be used to set the full scale output current of the DAC.
Ifs (mA) = 42.67 x REFIO/Rset
The voltage at REFIO is nominally set by the internal
bandgap at 1.235V. For a full scale output current of
20mA, the value of Rset is 2.635k.
Figure 4: AC Coupled Differential to
Single-ended Topology
DAC14135 Grounding Information
In the DAC14135, all the grounds AGND, REFLO, DGND
and CGND are shorted together inside the package. The
purpose of having separate grounds on the printed circuit
board is to prevent digital data currents from returning
through the analog or reference grounds, and corrupting
the analog outputs. Refer to the evaluation board layout.
http://www.national.com
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