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PDF ( 数据手册 , 数据表 ) DAC1232LCJ

零件编号 DAC1232LCJ
描述 DAC1231/DAC1232 12-Bit/ mP Compatible/Double-Buffered D to A Converters
制造商 National Semiconductor
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DAC1232LCJ 数据手册, 描述, 功能
February 1995
MICRO-DACTM DAC1208 DAC1209 DAC1210 DAC1230
DAC1231 DAC1232 12-Bit mP Compatible
Double-Buffered D to A Converters
General Description
The DAC1208 and the DAC1230 series are 12-bit multiply-
ing D to A converters designed to interface directly with a
wide variety of microprocessors (8080 8048 8085 Z-80
etc ) Double buffering input registers and associated con-
trol lines allow these DACs to appear as a two-byte ‘‘stack’’
in the system’s memory or I O space with no additional in-
terfacing logic required
The DAC1208 series provides all 12 input lines to allow sin-
gle buffering for maximum throughput when used with 16-bit
processors These input lines can also be externally config-
ured to permit an 8-bit data interface The DAC1230 series
can be used with an 8-bit data bus directly as it internally
formulates the 12-bit DAC data from its 8 input lines All of
these DACs accept left-justified data from the processor
The analog section is a precision silicon-chromium (Si-Cr)
R-2R ladder network and twelve CMOS current switches
An inverted R-2R ladder structure is used with the binary
weighted currents switched between the IOUT1 and IOUT2
maintaining a constant current in each ladder leg indepen-
dent of the switch state Special circuitry provides TTL logic
input voltage level compatibility
The DAC1208 series and DAC1230 series are the 12-bit
members of a family of microprocessor compatible DACs
(MICRO-DACsTM) For applications requiring other resolu-
tions the DAC1000 series for 10-bit and DAC0830 series
for 8-bit are available alternatives
Features
Y Linearity specified with zero and full-scale adjust only
Y Direct interface to all popular microprocessors
Y Double-buffered single-buffered or flow through digital
data inputs
Y Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y Works with g10V reference full 4-quadrant
multiplication
Y Operates stand-alone (without mP) if desired
Y All parts guaranteed 12-bit monotonic
Y DAC1230 series is pin compatible with the DAC0830
series 8-bit MICRO-DACs
Key Specifications
Y Current Settling Time
Y Resolution
Y Linearity (Guaranteed
over temperature)
Y Gain Tempco
Y Low Power Dissipation
Y Single Power Supply
1 ms
12 Bits
10 11 or 12 Bits of FS
1 3 ppm C
20 mW
5 VDC to 15 VDC
Typical Application
TRI-STATE is a registered trademark of National Semiconductor Corp
MICRO-DACTM is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL H 5690
TL H 5690 – 1
RRD-B30M115 Printed in U S A







DAC1232LCJ pdf, 数据表
Application Hints (Continued)
1 4 Left-Justified Data Format
It is important to realize that the input registers of these
DACs are arranged to accept a left-justified data word from
the microprocessor with the most significant 8 bits coming
first (Byte 1) and the lower 4 bits second Left justification
simply means that the binary point is assumed to be located
to the left of the most significant bit Figure 3 shows how the
12 bits of DAC data should be arranged in 2 8-bit registers
of an 8-bit processor before being written to the DAC
TL H 5690-10
X e don’t care
FIGURE 3 Left-Justified Data Format
1 5 16-Bit Data Bus Interface
The DAC1208 series provides all 12 digital input lines to
permit a direct parallel interface to a 16-bit data bus In this
instance double buffering is not always necessary (unless a
simultaneous updating of several DACs or a data transfer
via an external strobe is desired) so the 12-bit DAC register
can be wired to flow-through whereby its Q outputs always
reflect the state of its D inputs The external connections
required and the timing diagram for this single buffered ap-
plication are shown in Figure 4 Note that either left or right-
justified data from the processor can be accommodated
with a 16-bit data bus
1 6 Flow-Through Operation
Through primarily designed to provide microprocessor inter-
face compatibility the MICRO-DACs can easily be config-
ured to allow the analog output to continuously reflect the
state of an applied digital input This is most useful in appli-
Interface Timing
XFER and WR2 grounded Byte 1 Byte 2 tied to VCC
FIGURE 4 16-Bit Data Bus Interface for the DAC1208 Series
8
TL H 5690-11







DAC1232LCJ equivalent, schematic
Ordering Information
Part Number
DAC1208LCJ
DAC1208LCJ-1
DAC1209LCJ
DAC1210LCJ
DAC1210LCJ-1
DAC1230LCJ
DAC1230LCJ-1
DAC1231LCJ
DAC1231LCJ-1
DAC1231LCN
DAC1231LCWM
DAC1231LIN
DAC1232LCJ
DAC1232LCJ-1
DAC1232LCN
DAC1232LCWM
DAC1232LIN
Non-Linearity
0 018%
0 018%
0 024%
0 050%
0 050%
0 018%
0 018%
0 024%
0 024%
0 024%
0 024%
0 024%
0 050%
0 050%
0 050%
0 050%
0 050%
Package
J24A Cerdip
J24A Cerdip
J24A Cerdip
J24A Cerdip
J24A Cerdip
J20A Cerdip
J20A Cerdip
J20A Cerdip
J20A Cerdip
N20A Plastic
M20B SO
N20A Plastic
J20A Cerdip
J20A Cerdip
N20A Plastic
M20B SO
N20A Plastic
Temperature
Range
b40 C to a85 C
0 C to a70 C
b40 C to a85 C
b40 C to a85 C
0 C to a70 C
b40 C to a85 C
0 C to a70 C
b40 C to a85 C
0 C to a70 C
0 C to a70 C
0 C to a70 C
b40 C to a85 C
b40 C to a85 C
0 C to a70 C
0 C to a70 C
0 C to a70 C
b40 C to a85 C
16










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