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PDF ( 数据手册 , 数据表 ) DAC1221

零件编号 DAC1221
描述 16-Bit Low Power DIGITAL-TO-ANALOG CONVERTER
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 


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DAC1221 数据手册, 描述, 功能
®
DAC1221
DAC1221
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit Low Power
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 16-BIT MONOTONICITY GUARANTEED
OVER –40°C TO +85°C
q LOW POWER: 1.2mW
q VOLTAGE OUTPUT
q SETTLING TIME: 2ms to 0.012%
q MAX LINEARITY ERROR: 30ppm
q ON-CHIP CALIBRATION
DESCRIPTION
The DAC1221 is a Digital-to-Analog (D/A) converter
offering 16-bit monotonic performance over the speci-
fied temperature range. It utilizes delta-sigma technol-
ogy to achieve inherently linear performance in a
small package at very low power. The output range is
two times the external reference voltage. On-chip
calibration circuitry dramatically reduces offset and
gain errors.
APPLICATIONS
q PROCESS CONTROL
q ATE PIN ELECTRONICS
q CLOSED-LOOP SERVO-CONTROL
q SMART TRANSMITTERS
q PORTABLE INSTRUMENTS
q VCO CONTROL
The DAC1221 features a synchronous serial interface.
In single converter applications, the serial interface can
be accomplished with just two wires, allowing low-
cost isolation. For multiple converters, a CS signal
allows for selection of the appropriate D/A converter.
The DAC1221 has been designed for closed-loop
control applications in the industrial process control
market, and high resolution applications in the test and
measurement market. It is also ideal for remote appli-
cations, battery-powered instruments, and isolated sys-
tems. The DAC1221 is available in a SSOP-16 package.
XIN XOUT VREF
C1 C2A C2B C3
Clock Generator
Microcontroller
Instruction Register
Command Register
Data Register
Offset Register
Full-Scale Register
SDIO
SCLK
Serial
Interface
Second-Order
∆∑
Modulator
First-Order
Switched
Capacitor Filter
Second-Order
Continuous
Time Post Filter
Modulator Control
VOUT
CS
DVDD
DGND
AVDD
AGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1519B
1
DAPCrint1ed2in2U1.S.A. May, 2000
®







DAC1221 pdf, 数据表
DAC1221 operation mode, settling mode and data format.
The Data Input Register (DIR) contains the value for the
next conversion. The Offset and Full-Scale Calibration Reg-
isters (OCR and FCR) contain data used for correcting the
internal conversion value after it is placed into the DIR. The
data in these two registers may be the result of a calibration
routine, or they may be values which have been written
directly via the serial interface.
INSTRUCTION REGISTER (INSR)
Each serial communication starts with the 8 bits of INSR
being sent to the DAC1221. The read/write bit, the number
of bytes (n), and the starting register address are defined in
Table II. When the n bytes have been transferred, the
instruction is complete. A new communication cycle is
initiated by sending a new INSR (under restrictions outlined
in the Interfacing section).
MSB
LSB
R/W MB1 MB0
0
A3 A3 A1 A0
NOTE: INSR is a write-only register with the MSB (Most Significant Byte and
Bit) written first, independent of the BD bit.
TABLE II. Instruction Register.
R/W (Read/Write) Bit—For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
shown:
R/W
0
1
Write
Read
MB1, MB0 (Multiple Bytes) Bits—These two bits are used
to control the word length (number of bytes) of the read or
write operation, as shown:
MB1
0
0
1
MB0
0
1
0
1 Byte
2 Bytes
3 Bytes
A3 – A0 (Address) Bits—These four bits select the begin-
ning register location that will be read from or written to, as
shown in Table III. Each subsequent byte will be read from
or written to the next higher location (increment address). If
the BD bit in the Command register is set, each subsequent
byte will be read from or written to the next lower location
(decrement address). This bit does not affect INSR register
or the write operation for the CMR register. If the next
location is reserved in Table III, the results are unknown.
Reading or writing continues until the number of bytes
specified by MB1 and MB0 have been transferred.
A3 A2 A1 A0
0 0 0 0 Data Input Register Byte 1 MSB
0 0 0 1 Data Input Register Byte 0 LSB
0 0 1 0 Reserved
0 0 1 1 Reserved
0 1 0 0 Command Register Byte 1 MSB
0 1 0 1 Command Register Byte 0 LSB
0 1 1 0 Reserved
0 1 1 1 Reserved
1 0 0 0 Offset Cal Register Byte 2 MSB
1 0 0 1 Offset Cal Register Byte 1
1 0 1 0 Offset Cal Register Byte 0 LSB
1 0 1 1 Reserved
1 1 0 0 Full-Scale Cal Register Byte 2 MSB
1 1 0 1 Full-Scale Cal Register Byte 1
1 1 1 0 Full-Scale Cal Register Byte 0 LSB
1 1 1 1 Reserved
TABLE III. A3 - A0 Addressing.
COMMAND REGISTER (CMR)
The CMR controls all of the functionality of the DAC1221.
The new configuration is latched in on the negative transi-
tion of SCLK for the last bit of the last byte of data being
written to the command register. The organization of the
CMR is comprised of 16 bits of information in 2 bytes of 8
bits each.
MSB
Byte 1
ADPT CALPIN 1 0 1
Byte 0
0 CLR DF DISF BD
TABLE IV. Command Register.
0 CRST
MSB MD1
0
LSB
MD0
ADPT (Adaptive Filter Disable) Bit—The ADPT bit de-
termines if the adaptive filter is enabled or disabled. When
the Adaptive Filter is enabled, the DAC1221 does fast
settling only when there is an output step of larger than
40mV. For small changes in the data, fast settling is not
necessary. When ADPT = 1, the Adaptive Filter is disabled
and the DAC1221 will not look at the size of a step to
determine the necessity of using fast settling. In either case,
fast settling can be defeated if DISF = 1.
ADPT
0
1
Enabled (default)
Disabled
®
DAC1221
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