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PDF ( 数据手册 , 数据表 ) DAC1218

零件编号 DAC1218
描述 12-Bit Binary Multiplying D/A Converter
制造商 National Semiconductor
LOGO National Semiconductor LOGO 


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DAC1218 数据手册, 描述, 功能
December 1994
DAC1218 DAC1219
12-Bit Binary Multiplying D A Converter
General Description
The DAC1218 and the DAC1219 are 12-bit binary 4-quad-
rant multiplying D to A converters The linearity differential
non-linearity and monotonicity specifications for these con-
verters are all guaranteed over temperature In addition
these parameters are specified with standard zero and full-
scale adjustment procedures as opposed to the impractical
best fit straight line guarantee
This level of precision is achieved though the use of an
advanced silicon-chromium (SiCr) R-2R resistor ladder net-
work This type of thin-film resistor eliminates the parasitic
diode problems associated with diffused resistors and al-
lows the applied reference voltage to range from b25V to
25V independent of the logic supply voltage
CMOS current switches and drive circuitry are used to
achieve low power consumption (20 mW typical) and mini-
mize output leakage current errors (10 nA maximum)
Unique digital input circuitry maintains TTL compatible input
threshold voltages over the full operating supply voltage
range
The DAC1218 and DAC1219 are direct replacements for
the AD7541 series AD7521 series and AD7531 series with
a significant improvement in the linearity specification In
applications where direct interface of the D to A converter to
a microprocessor bus is desirable the DAC1208 and
DAC1230 series eliminate the need for additional interface
logic
Features
Y Linearity specified with zero and full-scale adjust only
Y Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y Works with g10V reference full 4-quadrant
multiplication
Y All parts guaranteed 12-bit monotonic
Key Specifications
Y Current Settling Time
Y Resolution
Y Linearity (Guaranteed
over temperature)
Y Gain Tempco
Y Low Power Dissipation
Y Single Power Supply
1 ms
12 Bits
12 Bits (DAC1218)
11 Bits (DAC1219)
1 5 ppm C
20 mW
5 VDC to 15 VDC
Typical Application
Connection Diagram
Dual-In-Line Package
 A1 A2 A3
VOUT e bVREF
aaa
248
where AN e 1 if digital input is high
AN e 0 if digital input is low
Ordering Information
JA12
4096
Temperature Range
Non
Linearity
0 012%
0 024%
0 C to a70 C
DAC1218LCJ-1
TL H 5691 – 1
b40 C to a85 C
DAC1218LCJ
DAC1219LCJ
TL H 5691 – 15
Top View
Package Outline
J18A Cerdip
J18A Cerdip
BI-FETTM is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL H 5691
RRD-B30M115 Printed in U S A







DAC1218 pdf, 数据表
Application Hints (Continued)
3 0 OBTAINING A BIPOLAR OUTPUT VOLTAGE
FROM A FIXED REFERENCE
The addition of a second op amp to the circuit of Figure 2
can generate a bipolar output voltage from a fixed reference
voltage (Figure 7 ) This in effect gives sign significance to
the MSB of the digital input word to allow two quadrant mul-
tiplication of the reference voltage The polarity of the refer-
ence voltage can also be reversed to realize full 4-quadrant
multiplication
The output responds in accordance to the following expres-
sion
 JD b 2048
VO e VREF
2048
0 s D s 4095
where D is the decimal equivalent of the true binary input
word This configuration inherently accepts a code (half-
scale or De2048) to provide 0V out without requiring an
external LSB offset as needed by other bipolar multiply-
ing DAC circuits
Only the offset voltage of amplifier A1 need be nulled to
preserve linearity The gain setting resistors around A2 must
match and track each other A thin film 4-resistor network
available from Beckman Instruments Inc (part no 694-3-
R10K-D) is ideally suited for this application Two of the four
resistors can be paralleled to form R and the other two can
be used separately as the resistors labeled 2R
Operation is summarized in the table below
MSB
Applied
Digital Input
Decimal
Equivalent
LSB
aVREF
VOUT
bVREF
1 1111111111 1
1 1000000000 0
1 0000000000 0
0 1111111111 1
0 1000000000 0
0 0000000000 0
4095
3072
2048
2047
1024
0
VREFb1 LSB
VREF 2
0
b1 LSB
bVREF 2
bVREF
lb VREF a1 LSB
blVREFl 2
0
a1 LSB
alVREFl 2
a lVREFl
Where 1 LSB e lVREFl
2048
0 1% matching
FIGURE 7 Obtaining a Bipolar Output from a Fixed Reference
TL H 5691 – 9
8














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