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PDF ( 数据手册 , 数据表 ) DAC10GS

零件编号 DAC10GS
描述 10-Bit High Speed Multiplying D/A Converter Universal Digital Logic Interface
制造商 Analog Devices
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DAC10GS 数据手册, 描述, 功能
a 10-Bit High Speed Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC10*
FEATURES
Fast Settling: 85 ns
Low Full-Scale Drift: 10 ppm/؇C
Nonlinearity to 0.05% Max Over Temperature Range
Complementary Current Outputs: 0 mA to 4 mA␣
Wide Range Multiplying Capability: 1 MHz Bandwidth
Wide Power Supply Range: +5, –7.5 Min to ؎18 V Max
Direct Interface to TTL, CMOS, ECL, PMOS, NMOS
Availability in Die Form␣
GENERAL DESCRIPTION
The DAC10 series of 10-bit monolithic multiplying digital-to-
analog converters provide high speed performance and full-scale
accuracy.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and low power consumption. Direct inter-
face to all popular logic families with full noise immunity is
provided by the high swing, adjustable threshold logic inputs.
All DAC10 series models guarantee full 10-bit monotonicity,
and nonlinearities as tight as +0.05% over the entire operating
temperature range are available. Device performance is essen-
tially unchanged over the ± 18 V power supply range, with
85 mW power consumption attainable at lower supplies.
A highly stable, unique trim method is used, which selectively
shorts Zener diodes, to provide 1/2 LSB full-scale accuracy
without the need for laser trimming.
Single-chip reliability, coupled with low cost and outstanding
flexibility, make the DAC10 device an ideal building block for
A/D converters, Data Acquisition systems, CRT displays, pro-
grammable test equipment and other applications where low
power consumption, input/output versatility and long-term
stability are required.
VREF (+)
16
VREF (–)
17
V+
15
VLC
1
SIMPLIFIED SCHEMATIC
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
5 6 7 8 9 10 11 12 13 14
BIAS NETWORK
CURRENT SWITCHES
REFERENCE
AMPLIFIER
4
IOUT
2 IOUT
18
COMP
3
V–
*Protected by Patent Nos. 4,055,770, 4,056,740 and 4,092,639.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998







DAC10GS pdf, 数据表
DAC10
APPLICATIONS
+VREF
RREF
OPTIONAL RESISTOR
FOR OFFSET INPUTS
RIN 16
4 RL
0V
REQ = 800
RP 17
DAC10
RL
2
TYPICAL VALUES:
RIN = 1k
+VIN = 2V
1
REQ =
1+
RIN
1+
RP
1
RREF
NO CAP
Figure 18. Pulsed Reference Operation
Reference Amplifier Setup
The DAC10 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer-
ence current. The reference current may be fixed or may vary
from nearly zero to 2 mA. The full-scale output current is a
linear function of the reference current and is given by:
I FR
=
1023
1024
× 2 × IREF
where IREF equals current flowing into Pin 16.
In positive reference applications, an external positive reference
voltage forces current through R16 into the VREF (+) terminal
(Pin 16) of the reference amplifier. Alternatively, a negative
reference may be applied to VREF (–) at Pin 17; reference current
flows from ground through R16 into V(+) as in the positive
reference case. This negative reference connection has the ad-
vantage of a very high impedance presented at Pin 17. R17
(nominally equal to R16) is used to cancel bias current errors;
R17 may be eliminated with only a minor increase in error.
Bipolar references may be accommodated by offsetting VREF or
Pin 17. The negative common-mode range of the reference
amplifier is given by: VCM– = V– plus (IREF × 2 k) plus 2 V.
The positive common-mode range is V+ less 1.8 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5 V TTL logic supply is not recommended as
a reference. If a regulated power supply is used as a reference,
R16 should be split into two resistors with the junction bypassed
to ground with a 0.1 µF capacitor.
For most applications, the tight relationship between IREF and
IFS will eliminate the need for trimming IREF. If required, full-
scale trimming may be accomplished by adjusting the value of
R16, or by using a potentiometer for R16. An improved method
of full-scale trimming that eliminates potentiometer TC effect is
shown in the Recommended Full-Scale Adjustment circuit.
The reference amplifier must be compensated by using a capaci-
tor from Pin 18 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see section entitled Reference Amplifier Compensation for Mul-
tiplying Applications.
Multiplying Operation
The DAC10 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 mA to 4 µA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 2 mA.
Reference Amplifier Compensation for Multiplying Applications
AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 18 to V–. The value
of this capacitor depends on the impedance presented to Pin 16
for R16 values of 1.0 k, 2.5 kand 5.0 k, minimum values
of CC are 15 pF, 37 pF and 75 pF. Larger values of R16 require
proportionately increased values of CC for proper phase margin.
For fastest response to a pulse, low values of R16 enabling small
CC values should be used. If Pin 16 is driven by a high imped-
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated,
which will decrease overall bandwidth and slew rate. For R16 =
1 kand CC = 15 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 16 is
200 and CC = 0. This yields a reference slew rate of 16 mA/
µs, which is relatively independent of RIN and VIN values.
LOGIC INPUTS
The DAC10 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos-
sible by the large input swing capability, 2 µA logic input current
and completely adjustable logic threshold voltage. For V– = –15 V,
the logic inputs may swing between –5 and +18 V. This enables
direct interface with +15 V CMOS logic, even when the DAC10
is powered from a +5 V supply. Minimum input logic swing and
minimum logic threshold voltage are given by: V– plus (lREF ×
2 k) plus 3 V. The logic threshold may be adjusted over a wide
range by placing an appropriate voltage at the logic threshold
control Pin (Pin 1, VLC). The appropriate graph shows the
relationship between VLC and VTH over the temperature range,
with VTH nominally 1.4 V above VLC. For TTL interface, simply
ground Pin 1. When interfacing ECL, an IREF = 1 mA is recom-
mended. For interfacing other logic families, see Figure 17. For
general setup of the logic control circuit, it should be noted that
Pin 1 will sink 1.1 mA typical; external circuitry should be de-
signed to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low imped-
ance. If Pin 1 is connected to a 1 kdivider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.
–8– REV. D














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