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PDF ( 数据手册 , 数据表 ) DAC1006LCN

零件编号 DAC1006LCN
描述 P Compatible/ Double-Buffered D to A Converters
制造商 National Semiconductor
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DAC1006LCN 数据手册, 描述, 功能
January 1995
DAC1006 DAC1007 DAC1008 mP Compatible
Double-Buffered D to A Converters
General Description
The DAC1006 7 8 are advanced CMOS Si-Cr 10- 9- and
8-bit accurate multiplying DACs which are designed to inter-
face directly with the 8080 8048 8085 Z-80 and other pop-
ular microprocessors These DACs appear as a memory lo-
cation or an I O port to the mP and no interfacing logic is
needed
These devices combined with an external amplifier and
voltage reference can be used as standard D A converters
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at-
tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control
All of these DACs are double buffered They can load all 10
bits or two 8-bit bytes and the data format is left justified
The analog section of these DACs is essentially the same
as that of the DAC1020
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC’s (MICRO-DACTM’s) For
applications requiring other resolutions the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail-
able alternatives
Part
Accuracy Pin Description
(bits)
DAC1006
DAC1007
DAC1008
10
9
8
For left-
20 justified
data
MICRO-DACTM and BI-FETTM are trademarks of National Semiconductor Corp
Features
Y Uses easy to adjust END POINT specs NOT BEST
STRAIGHT LINE FIT
Y Low power consumption
Y Direct interface to all popular microprocessors
Y Integrated thin film on CMOS structure
Y Double-buffered single-buffered or flow through digital
data inputs
Y Loads two 8-bit bytes or a single 10-bit word
Y Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y Works with g10V reference full 4-quadrant multiplica-
tion
Y Operates STAND ALONE (without mP) if desired
Y Available in 0 3 standard 20-pin package
Y Differential non-linearity selection available as special
order
Key Specifications
Y Output Current Settling Time
Y Resolution
Y Linearity
Y Gain Tempco
Y Low Power Dissipation
(including ladder)
Y Single Power Supply
500 ns
10 bits
10 9 and 8 bits
(guaranteed over temp )
b0 0003% of FS C
20 mW
5 to 15 VDC
Typical Application
DAC1006 1007 1008
C1995 National Semiconductor Corporation TL H 5688
NOTE FOR DETAILS OF BUS
CONNECTION SEE SECTION 6 0
TL H 5688 – 1
RRD-B30M115 Printed in U S A







DAC1006LCN pdf, 数据表
4 2 Op Amp Bias Current Input Leads
The op amp bias current (IB) CAN CAUSE DC ERRORS BI-
FETTM op amps have very low bias current and therefore
the error introduced is negligible BI-FET op amps are
strongly recommended for these DACs
The distance from the IOUT1 pin of the DAC to the inverting
input of the op amp should be kept as short as possible to
prevent inadvertent noise pickup
5 0 ANALOG APPLICATIONS
The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode
The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC The
analog functioning is reviewed here for completeness For
additional analog applications such as multipliers attenua-
tors digitally controlled amplifiers and low frequency sine
wave oscillators refer to the DAC1020 data sheet Some
basic circuit ideas are presented in this section in addition to
complete applications circuits
5 1 Operation in Current Switching Mode
The analog circuitry Figure 2 consists of a silicon-chromi-
um (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip As a result there is no
parasitic diode connected to the VREF pin as would exist if
diffused resistors were used The reference voltage input
(VREF) can therefore range from b10V to a10V
The digital input code to the DAC simply controls the posi-
tion of the SPDT current switches SW0 to SW9 A logical 1
digital input causes the current switch to steer the avail-
able ladder current to the IOUT1 output pin These MOS
switches operate in the current mode with a small voltage
drop across them and can therefore switch currents of ei-
ther polarity This is the basis for the 4-quadrant multiplying
feature of this DAC
5 1 1 Providing a Unipolar Output Voltage with the
DAC in the Current Switching Mode
A voltage output is provided by making use of an external
op amp as a current-to-voltage converter The idea is to use
the internal feedback resistor RFB from the output of the
op amp to the inverting (b) input Now when current is
entered at this inverting input the feedback action of the op
amp keeps that input at ground potential This causes the
applied input current to be diverted to the feedback resistor
The output voltage of the op amp is forced to a voltage
given by
VOUT e b(IOUT1cRFB)
Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor
In current switching mode applications both current output
pins (IOUT1 and IOUT2) should be operated at 0 VDC This is
accomplished as shown in Figure 3 The capacitor CC is
used to compensate for the output capacitance of the DAC
and the input capacitance of the op amp The required feed-
back resistor RFB is available on the chip (one end is inter-
nally tied to IOUT1) and must be used since an external
resistor will not provide the needed matching and tempera-
ture tracking This circuit can therefore be simplified as
DIGITAL INPUT CODE
FIGURE 2 Current Mode Switching
OP AMP CC pF Rj ts mS
TL H 5688 – 10
FIGURE 3 Converting IOUT to VOUT LF356 22 % 3
LF351 24 % 4
LF357 10 2 4k 1 5
8







DAC1006LCN equivalent, schematic
TL H 5688 – 21
FIGURE 17 Input Connections and Logic for DAC1006 1007 1008 with 16-Bit Data Bus
Three operating modes are possible flow through single
buffered or double buffered The timing diagrams for these
are shown below
6 3 1 Single Buffered
DAC1006 1007 1008 (20-Pin Parts)
6 4 Stand Alone Operation
For applications for a DAC which are not under mP control
(stand alone) there are two basic operating modes single
buffered and double buffered The timing diagrams for these
are shown below
6 4 1 Single Buffered
DAC1006 1007 1008 (20-Pin Parts)
6 3 2 Double Buffered
DAC1006 1007 1008 (20-Pin Parts)
6 4 2 Double Buffered
DAC1006 1007 1008 (20-Pin Parts)
TL H 5688–22
For a connection diagram of this operating mode use Figure 16 for the Logic and Figure 17 for the Data Input connections
TL H 5688 – 23
16










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