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PDF ( 数据手册 , 数据表 ) DAC0832LCJ

零件编号 DAC0832LCJ
描述 8-Bit P Compatible/ Double-Buffered D to A Converters
制造商 National Semiconductor
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DAC0832LCJ 数据手册, 描述, 功能
May 1999
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DAC).
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.
n Works with ±10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Key Specifications
n Current settling time: 1 µs
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
BI-FETand MICRO-DACare trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 1999 National Semiconductor Corporation DS005608
DS005608-1
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DAC0832LCJ pdf, 数据表
Typical Performance Characteristics (Continued)
Gain and Linearity Error
Variation vs. Supply Voltage
Write Pulse Width
Data Hold Time
DS005608-29
DAC0830 Series Application Hints
These DAC’s are the industry’s first microprocessor compat-
ible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility from
a digital control point of view. This 20-pin device is also pin
for pin compatible (with one exception) with the DAC1230, a
12-bit MICRO-DAC. In the event that a system’s analog out-
put resolution and accuracy must be upgraded, substituting
the DAC1230 can be easily accomplished. By tying address
bit A0 to the ILE pin, a two-byte µP write instruction (double
precision) which automatically increments the address for
the second byte write (starting with A0=“1”) can be used.
This allows either an 8-bit or the 12-bit part to be used with
no hardware or software changes. For the simplest 8-bit ap-
plication, this pin should be tied to VCC (also see other uses
in section 1.1).
Analog signal control versatility is provided by a precision
R-2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC’s is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8-bit
latching registers before being applied to the R-2R ladder
network to change the analog output. The addition of a sec-
ond register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more im-
portant, double-buffering allows any number of DAC’s in a
system to be updated to their new analog output levels si-
multaneously via a common strobe signal.
DS005608-30
DS005608-31
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit “write-only”
memory locations that provide an analog output quantity. All
inputs to these DAC’s meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in
non-microprocessor based systems. To prevent damage to
the chip from static discharge, all unused digital inputs
should be tied to VCC or ground. If any of the digital inputs
are inadvertantly left floating, the DAC interprets the pin as a
logic “1”.
1.1 Double-Buffered Operation
Updating the analog output of these DAC’s in a
double-buffered manner is basically a two step or double
write operation. In a microprocessor system two unique sys-
tem addresses must be decoded, one for the input latch con-
trolled by the CS pin and a second for the DAC latch which
is controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC’s. The timing for this operation is shown,
Figure 3.
It is important to note that the analog outputs that will change
after a simultaneous transfer are those from the DAC’s
whose input register had been modified prior to the XFER
command.
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DAC0832LCJ equivalent, schematic
DAC0830 Series Application Hints (Continued)
DS005608-14
FIGURE 15. Single Supply DAC with Level Shift and Span-
Adjustable Output
Gain and Linearity Error
Variation vs. Supply Voltage
Gain and Linearity Error
Variation vs. Reference Voltage
DS005608-32
Note: For these curves, VREF is the voltage applied to pin 11 (IOUT1) with
pin 12 (IOUT2) grounded.
FIGURE 16.
FIGURE 17.
DS005608-33
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