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PDF ( 数据手册 , 数据表 ) DA28F320S5-90

零件编号 DA28F320S5-90
描述 WORD-WIDE FlashFile MEMORY FAMILY
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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DA28F320S5-90 数据手册, 描述, 功能
E
ADVANCE INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S5, 28F320S5
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers
2 µs per Byte Effective
Programming Time
n Operating Voltage
5V VCC
5V VPP
n 70 ns Read Access Time (16 Mbit)
90 ns Read Access Time (32 Mbit)
n High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n System Performance Enhancements
STS Status Output
n Industry-Standard Packaging
SSOP and TSOP (16 Mbit)
SSOP (32 Mbit)
n Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n 100,000 Block Erase Cycles
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Configurable x8 or x16 I/O
n Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, nonvolatile, read/write storage
solutions for a wide range of applications. The word-wide memories are available at various densities in the
same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly
flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend
capabilities provide an ideal solution for code or data storage applications. For secure code storage
applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM,
the word-wide memories offer three levels of protection: absolute protection with VPP at GND, selective block
locking, and program/erase lockout during power transitions. These alternatives give designers ultimate
control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead
TSOP package.
June 1997
Order Number: 290609-001







DA28F320S5-90 pdf, 数据表
28F160S5, 28F320S5
E
28F016SA 28F160S3
28F016SV 28F160S5
3/5#
CE1#
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0#
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
NC
CE1#
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0#
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Highlights pinout changes.
56-LEAD TSOP
STANDARD PINOUT
14 mm x 20 mm
TOP VIEW
Figure 2. 28F160S5 TSOP 56-Lead Pinout
28F160S3 28F016SA
28F160S5 28F016SV
56 WP# WP#
55 WE# WE#
54 OE# OE#
53 STS RRYY//BBYY##
52
DQ15
DQ15
51
DQ7
DQ7
50
DQ14
DQ14
49
DQ6
DQ6
48 GND GND
47
DQ13
DQ13
46
DQ5
DQ5
45
DQ12
DQ12
44
DQ4
DQ4
43
VCC
VCC
42 GND GND
41
DQ11
DQ11
40
DQ3
DQ3
39
DQ10
DQ10
38
DQ2
DQ2
37
VCC
VCC
36
DQ9
DQ9
35
DQ1
DQ1
34
DQ8
DQ8
33
DQ0
DQ0
32 A0 A0
31 BYTE# BYTE#
30 NC NC
29 NC NC
0608_02
8 ADVANCE INFORMATION







DA28F320S5-90 equivalent, schematic
28F160S5, 28F320S5
E
4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started block
erase, program, or lock-bit configuration, the device
will not recognize the Read Array command until
the WSM completes its operation—unless the WSM
is suspended via an Erase-Suspend or Program-
Suspend command. The Read Array command
functions independently of the VPP voltage.
4.2 Read Query Mode Command
This section defines the data structure or
“database” returned by the Common Flash Interface
(CFI) Query command. System software should
parse this structure to gain critical information such
as block size, density, x8/x16, and electrical
specifications. Once this information has been
obtained, the software will know which command
sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query
is part of an overall specification for multiple
command set and control interface descriptions
called Common Flash Interface, or CFI.
4.2.1
QUERY STRUCTURE OUTPUT
The Query “database” allows system software to
gain critical information for controlling the flash
component. This section describes the device’s
CFI-compliant interface that allows the host system
to access Query data.
Query data are always presented on the lowest-
order data outputs (DQ0-7) only. The numerical
offset value is the address relative to the maximum
bus width supported by the device. On this device,
the Query table device starting address is a 10h
word address, since the maximum bus width is x16.
For this word-wide (x16) device, the first two bytes
of the Query structure, “Q” and ”R” in ASCII, appear
on the low byte at word addresses 10h and 11h.
This CFI-compliant device outputs 00H data on
upper bytes. Thus, the device outputs ASCII “Q” in
the low byte (DQ0-7) and 00h in the high byte
(DQ8-15).
Since the device is x8/x16 capable, the x8 data is
still presented in word-relative (16-bit) addresses.
However, the “fill data” (00h) is not the same as
driven by the upper bytes in the x16 mode. As in
x16 mode, the byte address (A0) is ignored for
Query output so that the “odd byte address” (A0
high) repeats the “even byte address” data (A0 low).
Therefore, in x8 mode using byte addressing, the
device will output the sequence “Q”, “Q”, “R”, “R”,
“Y”, “Y”, and so on, beginning at byte-relative
address 20h (which is equivalent to word offset 10h
in x16 mode).
At Query addresses containing two or more bytes
of information, the least significant data byte is
presented at the lower address, and the most
significant data byte is presented at the higher
address.
16 ADVANCE INFORMATION










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