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PDF ( 数据手册 , 数据表 ) DA28F016SV-070

零件编号 DA28F016SV-070
描述 16-MBIT (1 MBIT x 16/ 2 MBIT x 8) FlashFile MEMORY
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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DA28F016SV-070 数据手册, 描述, 功能
E
28F016SV
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
FlashFile™ MEMORY
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
User-Selectable 3.3V or 5V VCC
User-Selectable 5V or 12V VPP
n 65 ns Access Time
n 1 Million Erase Cycles per Block
n 30.8 MB/sec Burst Write Transfer Rate
n 0.48 MB/sec Sustainable Write Transfer
Rate
n Configurable x8 or x16 Operation
n 56-Lead TSOP and SSOP Type I
Packages
n Backwards-Compatible with 28F016SA,
28F008SA Command Set
n Revolutionary Architecture
Multiple Command Execution
Program during Erase
Command Super-Set of the Intel
28F008SA
Page Buffer Program
n 2 µA Typical Deep Power-Down
n 32 Independently Lockable Blocks
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016SV 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power operation, user-selectable VPP voltage and high read/program performance, the
28F016SV enables the design of truly mobile, high-performance personal computing and communications
products.
The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and
28F016SA 16-Mbit FlashFile memories), extended cycling, flexible VCC and VPP voltage (SmartVoltage
technology), fast program and read performance and selective block locking, provide a highly-flexible memory
component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives.
The 28F016SV’s dual read voltage enables the design of memory cards which can be read/written in 3.3V
and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor
interface. The flexible block locking option enables bundling of executable application software in a Resident
Flash Array or memory card. The 28F016SV is manufactured on Intel’s 0.6 µm ETOX IV process technology.
July 1997
Order Number: 290528-007
7/11/97 11:03 AM 29052807.DOC







DA28F016SV-070 pdf, 数据表
28F016SV FlashFile™ MEMORY
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve one
million Block Erase Cycles by providing wear-
leveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems and hard disk drive
designs.
The 28F016SV incorporates two Page Buffers of
256 bytes (128 words) each to allow page data
programs. This feature can improve a system
program performance by up to 4.8 times over
previous flash memory devices, which have no
Page Buffers.
All operations are started by a sequence of
Program commands to the device. Three Status
Registers (described in detail later in this
datasheet) and a RY/BY# output pin provide
information on the progress of the requested
operation.
While the 28F008SA requires an operation to
complete before the next operation can be
requested, the 28F016SV allows queuing of the
next operation while the memory executes the
current operation. This eliminates system
overhead when writing several bytes in a row to
the array or erasing several blocks at the same
time. The 28F016SV can also perform program
operations to one block of memory while
performing erase of another block.
The 28F016SV provides selectable block locking
to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S
or Application Code. Each block has an
associated nonvolatile lock-bit which determines
the lock status of the block. In addition, the
28F016SV has a master Write Protect pin (WP#)
which prevents any modifications to memory
blocks whose lock-bits are set.
The 28F016SV contains three types of Status
Registers to accomplish various functions:
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade
capability to the 28F016SV from a 28F008SA-
based design.
A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
8
E
32 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 5
and 6.
The 28F016SV incorporates an open drain
RY/BY# output pin. This feature allows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array.
Other configurations of the RY/BY# pin are
enabled via special CUI commands and are
described in detail in the 16-Mbit Flash Product
Family User’s Manual.
The 28F016SV’s enhanced Upload Device
Information command provides access to
additional information that the 28F016SA
previously did not offer. This command uploads
the Device Revision Number, Device Proliferation
Code and Device Configuration Code to the page
buffer. The Device Proliferation Code for the
28F016SV is 01H, and the Device Configuration
Code identifies the current RY/BY# configuration.
Section 4.4 documents the exact page buffer
address locations for all uploaded information. A
subsequent Page Buffer Swap and Page Buffer
Read command sequence is necessary to read
the correct device information.
The 28F016SV also incorporates a dual chip-
enable function with two input pins, CE0# and
CE1#. These pins have exactly the same
functionality as the regular chip-enable pin, CE#,
on the 28F008SA. For minimum chip designs,
CE1# may be tied to ground and system logic may
use CE0# as the chip enable input. The 28F016SV
uses the logical combination of these two signals
to enable or disable the entire chip. Both CE0# and
CE1# must be active low to enable the device. If
either one becomes inactive, the chip will be
disabled. This feature, along with the open drain
RY/BY# pin, allows the system designer to reduce
the number of control pins used in a large array of
16-Mbit devices.
The BYTE# pin allows either x8 or x16
read/programs to the 28F016SV. BYTE# at logic
low selects 8-bit mode with address A0 selecting
between the low byte and high byte. On the other
hand, BYTE# at logic high enables 16-bit
operation with address A1 becoming the lowest







DA28F016SV-070 equivalent, schematic
28F016SV FlashFile™ MEMORY
3.1 Extended Status Registers Memory Map
E
x8 MODE
RESERVED
GSR
RESERVED
BSR 31
RESERVED
RESERVED
.
.
.
A[20-0]
1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1F0000H
010002H
RESERVED
RESERVED
GSR
RESERVED
BSR 0
RESERVED
RESERVED
000006H
000005H
000004H
000003H
000002H
000001H
000000H
0528_05
Figure 5. Extended Status Register Memory
Map (Byte-Wide Mode)
x16 MODE
RESERVED
GSR
RESERVED
BSR 31
RESERVED
RESERVED
.
.
.
RESERVED
A[20-1]
F8003H
F8002H
F8001H
F8000H
08001H
RESERVED
GSR
RESERVED
BSR 0
RESERVED
RESERVED
00003H
00002H
00001H
00000H
0528_06
Figure 6. Extended Status Register Memory
Map (Word-Wide Mode)
16










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