DataSheet8.cn


PDF ( 数据手册 , 数据表 ) DA28F016SA-120

零件编号 DA28F016SA-120
描述 28F016SA 16-MBIT (1 MBIT X 16/ 2 MBIT X 8)FlashFile MEMORY
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


1 Page

No Preview Available !

DA28F016SA-120 数据手册, 描述, 功能
E
28F016SA 16-MBIT
(1 MBIT X 16, 2 MBIT X 8)
FlashFile™ MEMORY
Includes Commercial and Extended Temperature Specifications
n User-Selectable 3.3V or 5V VCC
n User-Configurable x8 or x16 Operation
n 70 ns Maximum Access Time
n 28.6 MB/sec Burst Write Transfer Rate
n 1 Million Typical Erase Cycles per
Block
n 56-Lead, 1.2 mm x 14 mm x 20 mm
TSOP Package
n 56-Lead, 1.8 mm x 16 mm x 23.7 mm
SSOP Package
n Revolutionary Architecture
Pipelined Command Execution
Program during Erase
Command Superset of Intel
28F008SA
n 1 mA Typical ICC in Static Mode
n 1 µA Typical Deep Power-Down
n 32 Independently Lockable Blocks
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA
enables the design of truly mobile, high-performance communications and computing products.
The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit
FlashFile memory), extended cycling, extended temperature operation, flexible VCC, fast program and read
performance and selective block locking provide highly flexible memory components suitable for Resident
Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage
enables the design of memory cards which can be interchangeably read/written in 3.3V and 5.0V systems. Its
x8/x16 architecture allows optimization of the memory-to-processor interface. Its high read performance and
flexible block locking enable both storage and execution of operating systems and application software.
Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective,
highest density monolithic 3.3V FlashFile memory.
November 1996
Order Number: 290489-004







DA28F016SA-120 pdf, 数据表
28F016SA
E
2.1 Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when the
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is
high).
A1–A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A6–15 selects 1 of 1024 rows, and A1–5 selects 16 of 512 columns. These
addresses are latched during data programs.
A16–A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These
addresses are latched during data programs, block erase and lock block
operations.
DQ0–DQ7
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is deselected or the outputs are
disabled.
DQ8–DQ15
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is
deselected or the outputs are disabled.
CE0#,CE1#
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE0# or CE1# high, the device
is deselected and power consumption reduces to standby levels upon
completion of any current data program or block erase operations. Both
CE0#, CE1# must be low to select the device.
All timing specifications are the same for both signals. Device selection
occurs with the latter falling edge of CE0# or CE1#. The first rising edge of
CE0# or CE1# disables the device.
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.
8







DA28F016SA-120 equivalent, schematic
28F016SA
E
4.4 28F016SA–Performance Enhancement Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Third Bus Cycle
Command
Mode Notes Oper Addr Data(12) Oper Addr Data(12) Oper Addr Data
Read Extended
Status Register
1 Write X xx71H Read RA GSRD
BSRD
Page Buffer Swap
7 Write X xx72H
Read Page Buffer
Write X
xx75H Read PBA
PD
Single Load to Page
Buffer
Write X
xx74H Write PBA
PD
Sequential Load to
Page Buffer
x8 4,6,10 Write X
xxE0H Write X
BCL Write X
BCH
x16 4,5,6,10 Write X
xxE0H Write X
WCL Write X
WCH
Page Buffer Write to
Flash
x8 3,4,9,10 Write
X
xx0CH Write A0 BC(L,H) Write PA BC(H,L)
x16 4,5,10 Write X
xx0CH Write X
WCL Write PA WCH
Two-Byte Program
Lock Block/Confirm
x8
3 Write X xxFBH Write A0 WD(L,H) Write PA WD(H,L)
Write X
xx77H Write BA xxD0H
Upload Status
Bits/Confirm
2 Write X xx97H Write X xxD0H
Upload Device
Information
Write X
xx99H Write X
xxD0H
Erase All Unlocked
Blocks/Confirm
Write X
xxA7H Write X
xxD0H
RY/BY# Enable to
Level-Mode
8 Write X xx96H Write X xx01H
RY/BY# Pulse-On-
Write
8 Write X xx96H Write X xx02H
RY/BY# Pulse-On-
Erase
8 Write X xx96H Write X xx03H
RY/BY# Disable
8 Write X xx96H Write X xx04H
Sleep
11 Write X
xxF0H
Abort
Write X
xx80H
ADDRESS
BA = Block Address
PBA = Page Buffer Address
RA = Extended Register Address
PA = Program Address
X = Don’t Care
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
16










页数 55 页
下载[ DA28F016SA-120.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
DA28F016SA-12028F016SA 16-MBIT (1 MBIT X 16/ 2 MBIT X 8)FlashFile MEMORYIntel Corporation
Intel Corporation

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap