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PDF ( 数据手册 , 数据表 ) DDC112

零件编号 DDC112
描述 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
制造商 Burr-Brown Corporation
LOGO Burr-Brown Corporation LOGO 


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DDC112 数据手册, 描述, 功能
®
For most current data sheet and other product
information, visit www.burr-brown.com
DDC112
DDC112
Dual Current Input 20-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q MONOLITHIC CHARGE MEASUREMENT ADC
q DIGITAL FILTER NOISE REDUCTION:
3.2ppm, rms
q INTEGRAL LINEARITY:
±0.005% Reading ±0.5ppm FSR
q HIGH PRECISION, TRUE INTEGRATING
FUNCTION
q PROGRAMMABLE FULL SCALE
q SINGLE SUPPLY
q CASCADABLE OUTPUT
APPLICATIONS
q DIRECT PHOTOSENSOR DIGITIZATION
q CT SCANNER DAS
q INFRARED PYROMETER
q PRECISION PROCESS CONTROL
q LIQUID/GAS CHROMATOGRAPHY
q BLOOD ANALYSIS
Protected by US Patent #5841310
DESCRIPTION
The DDC112 is a dual input, wide dynamic range,
charge-digitizing analog-to-digital converter (ADC) with
20-bit resolution. Low level current output devices,
such as photosensors, can be directly connected to its
inputs. Charge integration is continuous as each input
uses two integrators; while one is being digitized, the
other is integrating.
For each of its two inputs, the DDC112 combines
current-to-voltage conversion, continuous integration,
programmable full-scale range, A/D conversion, and
digital filtering to achieve a precision, wide dynamic
range digital result. In addition to the internal program-
mable full-scale ranges, external integrating capacitors
allow an additional user-settable full-scale range of up
to 1000pC.
To provide single-supply operation, the internal ADC
utilizes a differential input, with the positive input tied
to VREF. When the integration capacitor is reset at the
beginning of each integration cycle, the capacitor
charges to VREF. This charge is removed in proportion
to the input current. At the end of the integration cycle,
the remaining voltage is compared to VREF.
The high-speed serial shift register which holds the
result of the last conversion can be configured to allow
multiple DDC112 units to be cascaded, minimizing
interconnections. The DDC112 is available in a SO-28
package and is offered in two performance grades.
CAP1A
CAP1A
IN1
CAP1B
CAP1B
CAP2A
CAP2A
IN2
CAP2B
CAP2B
AVDD AGND
CHANNEL 1
Dual
Switched
Integrator
CHANNEL 2
Dual
Switched
Integrator
VREF
DVDD DGND
∆Σ
Modulator
DCLK
Digital
Filter
Digital
Input/Output
DVALID
DXMIT
DOUT
DIN
Control
RANGE2
RANGE1
RANGE0
TEST CONV CLK
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-14121D
DDC112Printed in U.S.A. January, 2000
®







DDC112 pdf, 数据表
CONV
CLK
SINTA
SINTB
SREF1
SREF2
SRESET
SA/D1A
Configuration of
Integrator A
VREF
Integrator A
Voltage Output
Convert
Wait
Integrate
Convert
Wait
FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3.
SINT
IN
SRESET
CF
a) Reset Configuration
SREF1
SREF2
SA/D
VREF
To Converter
IN
SINT
SRESET
CF
SINT
IN
SRESET
CF SREF1
SREF2
SA/D
c) Integrate Configuration
VREF b) Wait Configuration
To Converter
IN
SINT
SRESET
CF
SREF1
SREF2
SA/D
VREF
To Converter
SREF1
SREF2
SA/D
VREF
To Converter
d) Convert Configuration
FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112.
®
DDC112
8







DDC112 equivalent, schematic
Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC112 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does
allow flexibility in generating ncont mode CONV patterns.
For example, the DDC112 Evaluation Fixture operates in
the ncont mode by generating a square wave with pulse
width < t6. Figure 17 illustrates operation in the ncont mode
using a 50% duty cycle CONV signal with TINT = 1620
CLK periods. Care must be exercised when using a square
wave to generate CONV. There are certain integration
times that must be avoided since they produce very short
intervals for state 2 (or state 7 if CONV is inverted). As seen
in the state diagram, the state progresses from 2 to 3 as soon
as CONV is HIGH. The state machine does not insure that
the duration of state 2 is long enough to properly prepare the
next side for integration (t11). This must be done by the user
with proper timing of CONV. For example, if CONV is a
square wave with TINT = 3042 CLK periods, state 2 will
only be 18 CLK periods long, therefore, t11 will not be met.
CONV1
CONV2
mbsy
State
34
1
23
4
FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.
12
CONV
State
34
Integration
Status
mbsy
Int A Int B
1
DVALID
Side A
Data
234
Int A Int B
Side B
Data
FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.
®
DDC112
16
1
Side A
Data










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