DataSheet8.cn


PDF ( 数据手册 , 数据表 ) DD28F032SA-070

零件编号 DD28F032SA-070
描述 32-MBIT (2 MBIT X 16/ 4 MBIT X 8) FlashFile MEMORY
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


1 Page

No Preview Available !

DD28F032SA-070 数据手册, 描述, 功能
E
DD28F032SA
32-MBIT (2 MBIT X 16, 4 MBIT X 8)
FlashFile™ MEMORY
n User-Selectable 3.3V or 5V VCC
n User-Configurable x8 or x16 Operation
n 70 ns Maximum Access Time
n 28.6 MB/sec Burst Write Transfer Rate
n 1 Million Typical Erase Cycles per Block
n 56-Lead, 1.2 x 14 x 20 mm Advanced
Dual Die TSOP Package Technology
n 64 Independently Lockable Blocks
n Revolutionary Architecture
100% Backwards-Compatible with
Intel 28F016SA
Pipelined Command Execution
Program during Erase
n 2 mA Typical ICC in Static Mode
n 2 µA Typical Deep Power-Down
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and communication products. With innovative
capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal
choice for designing embedded mass storage flash memory systems.
The DD28F032SA is the result of highly-advanced packaging innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).
The DD28F032SA is the highest density, highest performance nonvolatile read/program solution for solid-
state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA
16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read
performance and selective block locking provide a highly flexible memory component suitable for high-density
memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The DD28F032SA’s dual read voltage
enables the design of memory cards which can be read/written in 3.3V and 5.0V systems interchangeably. Its
x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.
December 1996
Order Number: 290490-005







DD28F032SA-070 pdf, 数据表
DD28F032SA
E
2.1 Lead Descriptions
Symbol
A0
A1–A15
A16–A20
DQ0–DQ7
DQ8–DQ15
CE0#
CEX# =
CE1# or
CE2#
RP#
OE#
WE#
RY/BY#
Type
Name and Function
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is
high).
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A6-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512 columns. These
addresses are latched during data programs.
BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks in each of
the two 28F016SAs. These addresses are latched during data programs,
block erase and lock block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. CE0#/CE1# enable/disable the first
28F016SA (16 Mbit No. 1) while CE0#/CE2# enable/disable the second
28F016SA (16 Mbit No. 2). CE0# active low enables chip operation while
CE1# or CE2# select between the first and second device, respectively
CE1# and CE2# must not be active low simultaneously. Reference Table
3.0.
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE0#/CE1#/CE2# are high), except if a
RY/BY#
Pin Disable command is issued.
8







DD28F032SA-070 equivalent, schematic
DD28F032SA
E
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. A0 is automatically complemented to load the second byte of data. BYTE# must be at VIL.
The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.
6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.
9. Program address, PA, is the destination address in the flash array which must match the source address in the Page
Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual.
10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.
11. To ensure that the DD28F032SA’s power consumption during sleep mode reads the deep power-down current level, the
system also needs to de-select the chip by taking either or both CE0# or CE1#/CE2# high.
12. The upper byte of the data bus (DQ8–15) during command programs is a “Don’t Care” in x16 operation of the device.
5.5 Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
76543210
NOTES:
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
0 = Erase In Progress/Completed
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase
suspend, block erase or data program) before
the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA WRITE STATUS
1 = Error in Data Program
0 = Data Program Successful
If DWS and ES are set to “1” during a block
erase attempt, an improper command sequence
was entered. Clear the CSR and attempt the
operation again.
CSR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPPS bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The
WSM interrogates VPP’s level only after the Data
Program or Block Erase command sequences
have been entered, and informs the system if
VPP has not been switched on. VPPS is not
guaranteed to report accurate feedback between
VPPL and VPPH.
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
16










页数 30 页
下载[ DD28F032SA-070.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
DD28F032SA-07032-MBIT (2 MBIT X 16/ 4 MBIT X 8) FlashFile MEMORYIntel Corporation
Intel Corporation
DD28F032SA-07032-MBIT (2 MBIT X 16/ 4 MBIT X 8) FlashFile MEMORYIntel Corporation
Intel Corporation

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap