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PDF ( 数据手册 , 数据表 ) DAC8248

零件编号 DAC8248
描述 Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter
制造商 Analog Devices
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DAC8248 数据手册, 描述, 功能
a
Dual 12-Bit (8-Bit Byte)
Double-Buffered CMOS D/A Converter
DAC8248
FEATURES
Two Matched 12-Bit DACs on One Chip
12-Bit Resolution with an 8-Bit Data Bus
Direct Interface with 8-Bit Microprocessors
Double-Buffered Digital Inputs
RESET to Zero Pin
12-Bit Endpoint Linearity (؎1/2 LSB) Over Temperature
؉5 V to ؉15 V Single Supply Operation
Latch-Up Resistant
Improved ESD Resistance
Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin
SOL Package
Available in Die Form
PIN CONNECTIONS
24-Pin 0.3" Cerdip (W Suffix),
24-Pin Epoxy DIP (P Suffix),
24-Pin SOL (S Suffix)
APPLICATIONS
Multichannel Microprocessor-Controlled Systems
Robotics/Process Control/Automation
Automatic Test Equipment
Programmable Attenuator, Power Supplies, Window
Comparators
Instrumentation Equipment
Battery Operated Equipment
GENERAL DESCRIPTION
The DAC8248 is a dual 12-bit, double-buffered, CMOS digital-
to-analog converter. It has an 8-bit wide input data port that inter-
faces directly with 8-bit microprocessors. It loads a 12-bit word in
two bytes using a single control; it can accept either a least signifi-
cant byte or most significant byte first. For designs with a 12-bit or
16-bit wide data path, choose the DAC8222 or DAC8221.
The DAC8248’s double-buffered digital inputs allow both
DAC’s analog output to be updated simultaneously. This is par-
ticularly useful in multiple DAC systems where a common
LDAC signal updates all DACs at the same time. A single
RESET pin resets both outputs to zero.
The DAC8248’s monolithic construction offers excellent DAC-
to-DAC matching and tracking over the full operating tempera-
ture range. The DAC consists of two thin-film R-2R resistor
ladder networks, two 12-bit, two 8-bit, and two 4-bit data regis-
ters, and control logic circuitry. Separate reference input and
feedback resistors are provided for each DAC. The DAC8248
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703







DAC8248 pdf, 数据表
DAC8248
Four Cycle Update
Five Cycle Update
Write Timing Cycle Diagram
PARAMETER DEFINITIONS
RESOLUTION (N)
The resolution of a DAC is the number of states (2n) that the
full-scale range (FSR) is divided (or resolved) into; where n is
equal to the number of bits.
RELATIVE ACCURACY (INL)
Relative accuracy, or integral nonlinearity, is the maximum de-
viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.
DIFFERENTIAL NONLINEARITY (DNL)
Differential nonlinearity is the worst case deviation of any adja-
cent analog output from the ideal 1 LSB step size. The devia-
tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than ± 1 LSB may be nonmonotonic. ± 1/2 LSB
INL guarantees monotonicity and ± 1 LSB maximum DNL.
GAIN ERROR (GFSE)
Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
Refer to PMI 1990/91 Data Book, Section 11, for additional
digital-to-analog converter definitions.
GENERAL CIRCUIT DESCRIPTION
CONVERTER SECTION
The DAC8248 incorporates two multiplying 12-bit current out-
put CMOS digital-to-analog converters on one monolithic chip.
It contains two highly stable thin-film R-2R resistor ladder net-
works, two 12-bit DAC registers, two 8-bit input registers, and
two 4-bit input registers. It also contains the DAC control logic
circuitry and 24 single-pole, double-throw NMOS transistor
current switches.
Figure 1 shows a simplified circuit for the R-2R ladder and tran-
sistor switches for a single DAC. R is typically 11 k. The tran-
sistor switches are binarily scaled in size to maintain a constant
voltage drop across each switch. Figure 2 shows a single NMOS
transistor switch.
Figure 1. Simplified Single DAC Circuit Configuration.
(Switches Are Shown For All Digital Inputs at Zero)
–8– REV. B







DAC8248 equivalent, schematic
Figure 12. DAC8248 to MC6809 Interface
Figure 13. DAC8248 to MC68008 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Cerdip
(Q-24)
0.005 (0.13) MIN
0.098 (2.49) MAX
24 13
0.310 (7.87)
1
PIN 1
1.280 (32.51) MAX
0.220 (5.59)
12
0.060 (1.52)
0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0.015 (0.38)
0.150
(3.81)
MIN
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
24-Lead Plastic DIP
(N-24)
1.275 (32.30)
1.125 (28.60)
24
1
PIN 1
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
13 0.280 (7.11)
12 0.240 (6.10) 0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.060 (1.52)
0.115 (2.93)
0.015 (0.38)
0.150
(3.81)
MIN
0.070 (1.77) SEATING
0.045 (1.15) PLANE
0.015 (0.381)
0.008 (0.204)
24 Lead SOL
(R-24)
0.6141 (15.60)
0.5985 (15.20)
24 13
1 12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
8°
SEATING
PLANE
0°
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
–16–










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