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PDF ( 数据手册 , 数据表 ) DAC8143FS

零件编号 DAC8143FS
描述 12-Bit Serial Daisy-Chain CMOS D/A Converter
制造商 Analog Devices
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DAC8143FS 数据手册, 描述, 功能
a
12-Bit Serial Daisy-Chain
CMOS D/A Converter
DAC8143
FEATURES
Fast, Flexible, Microprocessor Interfacing in Serially
Controlled Systems
Buffered Digital Output Pin for Daisy-Chaining
Multiple DACs
Minimizes Address-Decoding in Multiple DAC
Systems—Three-Wire Interface for Any Number of DACs
One Data Line
One CLK Line
One Load Line
Improved Resistance to ESD
–40؇C to +85؇C for the Extended Industrial Temperature
Range
APPLICATIONS
Multiple-Channel Data Acquisition Systems
Process Control and Industrial Automation
Test Equipment
Remote Microprocessor-Controlled Systems
GENERAL INFORMATION
The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A
converter that features serial data input and buffered serial data
output. It was designed for multiple serial DAC systems, where
serially daisy-chaining one DAC after another is greatly simplified.
The DAC8143 also minimizes address decoding lines enabling
simpler logic interfacing. It allows three-wire interface for any
number of DACs: one data line, one CLK line and one load line.
Serial data in the input register (MSB first) is sequentially
clocked out to the SRO pin as the new data word (MSB first) is
simultaneously clocked in from the SRI pin. The strobe inputs
are used to clock in/out data on the rising or falling (user
selected) strobe edges (STB1, STB2, STB3, STB4).
When the shift register’s data has been updated, the new data
word is transferred to the DAC register with use of LD1 and
LD2 inputs.
Separate LOAD control inputs allow simultaneous output up-
dating of multiple DACs. An asynchronous CLEAR input
resets the DAC register without altering data in the input
register.
Improved linearity and gain error performance permits reduced
circuit parts count through the elimination of trimming compo-
nents. Fast interface timing reduces timing design considerations
while minimizing microprocessor wait states.
The DAC8143 is available in plastic packages that are compat-
ible with autoinsertion equipment.
Plastic packaged devices come in the extended industrial tem-
perature range of –40°C to +85°C.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
VREF
CLR
LD1
LD2
STB1
STB4
STB3
STB2
SRI
FUNCTIONAL BLOCK DIAGRAM
VDD
DAC8143
12-BIT
D/A CONVERTER
DAC REGISTER
LOAD
RFB
IOUT1
IOUT2
AGND
CLK
INPUT 12-BIT
SHIFT REGISTER
IN OUT
DGND
SRO
WR
DBX
P
ADDRESS BUS
ADDRESS
DECODER
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
Figure 1. Multiple DAC8143s with Three-Wire Interface
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999







DAC8143FS pdf, 数据表
DAC8143
Where RO is a function of the digital code, and:
RO = 10 kfor more than four bits of Logic 1,
RO = 30 kfor any single bit of Logic 1.
Therefore, the offset gain varies as follows:
at code 0011 1111 1111,
VERROR1
=
VOS
1+1100
kΩ
kΩ
=
2
VOS
at code 0100 0000 0000,
VERROR2
=
VOS
1 + 1300
kΩ
kΩ
=
4/3
VOS
The error difference is 2/3 VOS.
Since one LSB has a weight (for VREF = +10 V) of 2.4 mV for
the DAC8143, it is clearly important that VOS be minimized,
using either the amplifier’s pulling pins, an external pulling
network, or by selection of an amplifier with inherently low VOS.
Amplifiers with sufficiently low VOS include OP77, OP97, OP07,
OP27, and OP42.
INTERFACE LOGIC OPERATION
The microprocessor interface of the DAC8143 has been design-
ed with multiple STROBE and LOAD inputs to maximize inter-
facing options. Control signals decoding may be done on chip or
with the use of external decoding circuitry (see Figure 21).
Serial data is clocked into the input register and buffered output
stage with STB1, STB2, or STB4. The strobe inputs are active
on the rising edge. STB3 may be used with a falling edge clock
data.
Serial data output (SRO) follows the serial data input (SRI) by
12 clocked bits.
Holding any STROBE input at its selected state (i.e., STB1,
STB2 or STB4 at logic HIGH or STB3 at logic LOW) will act to
prevent any further data input.
When a new data word has been entered into the input register,
it is transferred to the DAC register by asserting both LOAD
inputs.
The CLR input allows asynchronous resetting of the DAC regis-
ter to 0000 0000 0000. This reset does not affect data held in
the input registers. While in unipolar mode, a CLEAR will
result in the analog output going to 0 V. In bipolar mode, the
output will go to –VREF.
INTERFACE INPUT DESCRIPTION
STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11)—Input Register
and Buffered Output Strobe. Inputs Active on Rising
Edge. Selected to load serial data into input register and buff-
ered output stage. See Table I for details.
STB3 (Pin 10)—Input Register and Buffered Output
Strobe Input. Active on Falling Edge. Selected to load serial
data into input register and buffered output stage. See Table I
for details.
LD1 (Pin 5), LD2 (Pin 9)—Load DAC Register Inputs.
Active Low. Selected together to load contents of input register
into DAC register.
CLR (Pin 13)—Clear Input. Active Low. Asynchronous.
When LOW, 12-bit DAC register is forced to a zero code (0000
0000 0000) regardless of other interface inputs.
WORD N –1
SRI
tDS1, tDS2, tDS3, tDS4
BIT 1
MSB
BIT 2
tDH1, tDH2, tDH3, tDH4
WORD N –2
BIT 12
LSB
BIT 1
MSB
BIT 2
tSR1
WORD N –1
SRO
* STROBE
(STB1, STB2, STB4)
BIT 1
MSB
BIT 2
tPD
12
tSTB1
tSTB2
tSTB3
tSTB4
tSTB1
tSTB2
tSTB3
tSTB4
BIT 1
MSB
BIT 2
12 1 2
tASB
tLD1
tLD2
LD1 AND LD2
LOAD NEW 12-BIT WORD INTO
INPUT REGISTER AND SHIFT
OUT PREVIOUS WORD
LOAD INPUT REGISTER'S
DATA INTO DAC REGISTER
NOTES:
* STROBE WAVEFORM IS INVERTED IF
STB3 IS USED TO STROBE SERIAL DATA
BITS INTO INPUT REGISTER.
** DATA IS STROBED INTO AND OUT OF
THE INPUT SHIFT REGISTER MSB FIRST.
Figure 15. Timing Diagram
WORD N
BIT 11
BIT 12
LSB
WORD N
BIT 12
LSB
BIT 1
LSB
11 12
–8– REV. C














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