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PDF ( 数据手册 , 数据表 ) DAC8043EZ

零件编号 DAC8043EZ
描述 12-Bit Serial Input Multiplying CMOS D/A Converter
制造商 Analog Devices
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DAC8043EZ 数据手册, 描述, 功能
a
FEATURES
12-Bit Accuracy in an 8-Pin Mini-DIP
Fast Serial Data Input
Double Data Buffers
Low ؎1/2 LSB Max INL and DNL
Max Gain Error: ؎1 LSB
Low 5 ppm/؇C Max Tempco
ESD Resistant
Low Cost
Available in Die Form
APPLICATIONS
Autocalibration Systems
Process Control and Industrial Automation
Programmable Amplifiers and Attenuators
Digitally-Controlled Filters
12-Bit Serial Input
Multiplying CMOS D/A Converter
DAC8043
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-pin mini-DIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. Also, improved linearity and gain error performance
permit reduced parts count through the elimination of trimming
components. Separate input clock and load DAC control lines
allow full user control of data loading and analog output.
The circuit consists of a 12-bit serial-in, parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC, and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
The DAC8043’s fast interface timing may reduce timing design
considerations while minimizing microprocessor wait states. For
applications requiring an asynchronous CLEAR function or more
versatile microprocessor interface logic, refer to the PM-7543.
Operating from a single +5 V power supply, the DAC8043 is
the ideal low power, small size, high performance solution to
many application problems. It is available in plastic and cerdip
packages that are compatible with auto-insertion equipment.
PIN CONNECTIONS
8-Pin Epoxy DIP
(P-Suffix)
8-Pin Cerdip
(Z-Suffix)
16-Lead Wide-Body SOL
(S-Suffix)
N.C. 1
16 N.C.
N.C. 2
15 N.C.
VREF 3
14 VDD
RFB 4 DAC8043 13 CLK
IOUT
5
TOP VIEW
(Not to Scale)
12
SRI
GND 6
11 LD
GND 7
10 N.C.
N.C. 8
9 N.C.
NC = NO CONNECT
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703







DAC8043EZ pdf, 数据表
DAC8043
The gain and phase stability of the output amplifier, board lay-
out, and power supply decoupling will all affect the dynamic
performance. The use of a small compensation capacitor may be
required when high-speed operational amplifiers are used. It
may be connected across the amplifier’s feedback resistor to
provide the necessary phase compensation to critically damp the
output. The DAC8043’s output capacitance and the RFB resis-
tor form a pole that must be outside the amplifier’s unity gain
crossover frequency.
The considerations when using high-speed amplifiers are:
1. Phase compensation (see Figures 5 and 6).
2. Power supply decoupling at the device socket and use of
proper grounding techniques.
Figure 6. Unipolar Operation with Fast Op Amp and Gain
Error Trimming (2-Quadrant)
APPLICATIONS INFORMATION
APPLICATION TIPS
In most applications, linearity depends upon the potential of
IOUT and GND (pins 3 and 4) being exactly equal to each other.
In most applications, the DAC is connected to an external op
amp with its noninverting input tied to ground (see Figures 5
and 6). The amplifier selected should have a low input bias cur-
rent and low drift over temperature. The amplifier’s input offset
voltage should be nulled to less than +200 µV (less than 10% of
1 LSB).
The operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. This resistor can
cause a variable offset voltage appearing as a varying output er-
ror. All grounded pins should tie to a single common ground
point, avoiding ground loops. The VDD power supply should
have a low noise level with no transients greater than +17 V.
UNIPOLAR OPERATION (2-QUADRANT)
The circuit shown in Figures 5 and 6 may be used with an ac or
dc reference voltage. The circuit’s output will range between 0 V
and approximately –VREF (4095/4096) depending upon the digital
input code. The relationship between the digital input and
Figure 5. Unipolar Operation with High Accuracy Op Amp
(2-Quadrant)
the analog output is shown in Table I. The limiting parameters
for the VREF range are the maximum input voltage range of the
op amp or ± 25 V, whichever is lowest.
Gain error may be trimmed by adjusting R1 as shown in Figure
6. The DAC register must first be loaded with all 1s. R1 may
then be adjusted until VOUT = –VREF (4095/4096). In the case of
an adjustable VREF, R1 and R2 may be omitted, with VREF ad-
justed to yield the desired full-scale output.
In most applications the DAC8043’s negligible zero scale error
and very low gain error permit the elimination of the trimming
components (R1 and the external R2) without adverse effects on
circuit performance.
Table I. Unipolar Code Table
Digital Input
MSB
LSB
Nominal Analog Output
(VOUT as shown in Figures 5 and 6)
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
4095
–VREF  4096
2049
–VREF  4096
–VREF
2048
 4096
=
VREF
2
2047
–VREF 4096
0000 0000 0001
0000 0000 0000
–VREF
1
 4096
0
–VREF  4096 = 0
NOTES
1Nominal full scale for the circuits of Figures 5 and 6 is given by
4095
FS = –VREF  4096
2Nominal LSB magnitude for the circuits of Figures 5 and 6 is given by
1
LSB = VREF  4096 or VREF (2–n).
–8– REV. C














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