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PDF ( 数据手册 , 数据表 ) LU6612-T64-DB

零件编号 LU6612-T64-DB
描述 LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX
制造商 Agere Systems
LOGO Agere Systems LOGO 


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LU6612-T64-DB 数据手册, 描述, 功能
Data Sheet
July 2000
LU6612 FASTCAT TM Single-FET
for 10Base-T/100Base-TX
Features
General
10 Mbits/s Transceiver
s Compatible with IEEE * 802.3u 10Base-T standard
for twisted-pair cable
s Autopolarity detection and correction
s Adjustable squelch level for extended wire line
length capability (2 levels)
s Interfaces with IEEE 802.3u media independent
interface (MII)
s On-chip filtering eliminates the need for external fil-
ters
s Half- and full-duplex operations
100 Mbits/s Transceiver
s Compatible with IEEE 802.3u MII (clause 22), PCS
(clause 23), PMA (clause 24), autonegotiation
(clause 28), and PMD (clause 25) specifications
s Scrambler/descrambler bypass
s Encoder/decoder bypass
s 3-statable MII in 100 Mbits/s mode
s Selectable carrier sense signal generation (CRS
asserted during either transmission or reception in
half duplex, CRS asserted during reception only in
full duplex)
s Selectable MII or 5-bit code group interface
s Half- or full-duplex operations
s On-chip filtering and adaptive equalization that
eliminates the need for external filters
s Autonegotiation (IEEE 802.3u clause 28):
— Fast link pulse (FLP) burst generator
— Arbitration function
— Accepts preamble suppression
— Operates up to 12.5 MHz
s Supports the station management protocol and
frame format (clause 22):
— Basic and extended registers
— Supports next-page function
— Accepts preamble suppression
— Operates up to 12.5 MHz
s Supports the following management functions via
pins if station management is unavailable:
— Speed select
— Encoder/decoder bypass
— Scrambler/descrambler bypass
— Full duplex
— Autonegotiation
s Supports half- and full-duplex operations
s Provides four status signals: receive/transmit activ-
ity, full duplex, link integrity, and speed indication
s Powerdown mode for 10 Mbits/s and 100 Mbits/s
operation
s Loopback for 10 Mbits/s and 100 Mbits/s operation
s 0.35 µm low-power CMOS technology
s 64-pin TQFP
s Single 5 V power supply
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.







LU6612-T64-DB pdf, 数据表
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Pin Information
Data Sheet
July 2000
VCCBG
ISET_100
GNDBG
LINKLED/PHYAD[0]
ACTLED/PHYAD[1]
VCCIOA
GNDIOA
TX
TY
GNDT
VCCT
CLKREF
GNDBT
VCCBT
TEST[0]
TEST[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LU6612
48 GNDDIGB
47 TX_CLK
46 RX_ER/RXD[4]
45 RX_DV
44 RX_CLK
43 COL
42 CRS
41 GNDIOC
40 RXD[0]
39 RXD[1]
38 RXD[2]
37 RXD[3]
36 GNDDIGA
35 VCCDIGA
34 TXD[0]
33 TXD[1]
Figure 5. LU6612 Pinout
5-5866.r2
8 Lucent Technologies Inc.







LU6612-T64-DB equivalent, schematic
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet
July 2000
MII Station Management (continued)
Table 10. MR1—Status Register Bit Descriptions
Bit1
1.15 (T4ABLE)
1.14 (TXFULDUP)
1.13 (TXHAFDUP)
1.12 (ENFULDUP)
1.11 (ENHAFDUP)
1.10:7
1.6 (NO_PA_OK)
1.5 (NWAYDONE)
1.4 (REM_FLT)
1.3 (NWAYABLE)
1.2 (LSTAT_OK)
1.1 (JABBER)
1.0 (EXT_ABLE)
Type2
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
100Base-T4 Ability. This bit will always be a 0.
0: Not able
1: Able
100Base-TX Full-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
100Base-TX Half-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
10Base-T Full-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
10Base-T Half-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
Reserved. All bits will read as a 0.
Suppress Preamble. This bit is set to a 1, indicating that the LU6612 accepts
management frames with the preamble suppressed. (This function is not sup-
ported by QS6611.)
Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation
process has been completed. The contents of registers MR4, MR5, MR6, and
MR7 are now valid. The default value is a 0. This bit is reset when autonegotia-
tion is started.
Remote Fault. When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. The default is a 0.
Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform
autonegotiation. The value of this bit is always a 1.
Link Status. When this bit is a 1, it indicates a valid link has been established.
This bit has a latching function: a link failure will cause the bit to clear and stay
cleared until it has been read via the management interface.
Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will
remain set until it is read, and the jabber condition no longer exists.
Extended Capability. This bit indicates that the LU6612 supports the extended
register set (MR2 and beyond). It will always read a 1.
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
16 Lucent Technologies Inc.










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