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PDF ( 数据手册 , 数据表 ) LU3X31T-T64

零件编号 LU3X31T-T64
描述 LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX
制造商 Agere Systems
LOGO Agere Systems LOGO 


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LU3X31T-T64 数据手册, 描述, 功能
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Overview
The LU3X31T-T64 is a fully integrated
10/100 Mbits/s physical layer device with an inte-
grated transceiver. It is provided in a 64-pin TQFP
package with low-power operation and powerdown
modes. Typical applications for this part are CardBus
and PCMCIA Ethernet products. Operating at 3.3 V,
the LU3X31T-T64 is a powerful device for the forward
migration of legacy 10 Mbits/s products and noncom-
pliant (does not have autonegotiation) 100 Mbits/s
devices. The LU3X31T-T64 was designed from the
beginning to conform fully with all pertinent specifica-
tions, from the ISO*/IEC 11801 and EIA/TIA 568
cabling guidelines to ANSIX3.263 TP-PMD to
IEEE § 802.3 Ethernet specifications.
Features
s Single-chip integrated physical layer and trans-
ceiver for 10Base-T and/or 100Base-T functions
s IEEE 802.3 compatible 10Base-T and 100Base-T
physical layer interface and ANSI X3.263 TP-PMD
compatible transceiver
s Built-in analog 10 Mbits/s receive filter, eliminating
the need for external filters
s Built-in 10 Mbits/s transmit filter
s 10 Mbits/s PLL exceeding tolerances for both pre-
amble and data jitter
s 100 Mbits/s PLL, combined with the digital adap-
tive equalizer, robustly handles variations in rise-
fall time, excessive attenuation due to channel
loss, duty-cycle distortion, crosstalk, and baseline
wander
s Transmit rise-fall time can be manipulated to pro-
vide lower emissions, amplitude fully compatible
for proper interoperability
s Programmable scrambler seed for better FCC
compliancy
s IEEE 802.3u Clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control
s Fully configurable via pins and management
accesses
s Extended management support with interrupt
capabilities
s PHY MIB support
s Symbol mode option
s Low-power operation: <150 mA max
s Low autonegotiation power: <30 mA
s Very low powerdown mode: <5 mA
s 64-pin TQFP package (10 mm x 10 mm x 1.4 mm)
* ISO is a registered trademark of The International Organization
for Standardization.
EIA is a registered trademark of The Electronic Industries Asso-
ciation.
ANSI is a registered trademark of The American National Stan-
dards Institute, Inc.
§ IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.







LU3X31T-T64 pdf, 数据表
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Pin Descriptions (continued)
Table 6. Autonegotiation Configuration (Refer to Table 11.) (continued)
Pin
No.
Pin Name
I/O
Pin Description
43 10HDEN/LEDFD I/O 10 Half-Duplex Enable. The logic level of this pin is detected at powerup or
reset to determine whether 10 Mbits/s half-duplex mode is available. When
autonegotiation is enabled, this input sets the ability register bit in advertise-
ment register 4. When autonegotiation is not enabled, this input will select
the mode of operation. This pin has an internal 40 kpull-up resistor. See
Table 7 for LEDFD description.
Note: Smaller font indicates that the pin has multiple functions.
Table 7. LED and Status Outputs
Pin
No.
Pin Name
I/O
Pin Description
40 LEDRX I/O Receive LED. This output will drive a 10 mA LED if the LU3X31T-T64 is
receiving data from the UTP cable. This pin has an internal 40 kpull-down
resistor. The LED should be connected as logic 0 configuration as shown in
Figure 5, without the 10 kresistor.
41 LEDTX/ACTLED/ I/O Transmit LED or Activity LED. When bit 7 of register 17h is 0, this output
BPSCR
will drive a 10 mA LED if the LU3X31T-T64 is transmitting data. If the control
bit is set, then the LED will be driven whenever receive or transmit activity is
present. This pin has an internal 40 kpull-down. The LED should be con-
nected as LOGIC 0 configuration in Figure 5 without the 10 kresistor. See
Table 5 for BPSCR description.
44 LNKLED/BPALIGN I/O Link LED. This output will drive a 10 mA LED for as long as a valid link
exists across the cable. Place a 10 kresistor across the LED pins if setting
to nondefault mode, i.e., bypass align mode as shown in Figure 5. See Table
5 for BPALIGN description.
42 LEDCOL/BP4B5B I/O Collision LED. This output will drive a 10 mA LED whenever the LU3X31T-
T64 senses a collision has occurred. Place a 10 kresistor across the LED
pins if setting to nondefault mode, i.e., bypass 4B/5B mode as shown in Fig-
ure 5. See Table 5 for BP4B5B description.
43 LEDFD/10HDEN I/O Full-Duplex Status. This output will drive a 10 mA LED when the LU3X31T-
T64 is in full-duplex mode. Place a 10 kresistor across the LED pins if set-
ting to nondefault mode, i.e., 10HD disable mode as shown in Figure 5. See
Table 6 for 10HDEN description.
17 LEDSP/10FDEN I/O Speed Status. This output will drive a 10 mA LED when the LU3X31T-T64
is in 100 Mbits/s mode. Place a 10 kresistor across the LED pins if setting
to nondefault mode, i.e., 10FD disable mode as shown in Figure 5. See
Table 6 for 10FDEN description.
Note: Smaller font indicates that the pin has multiple functions.
8 Lucent Technologies Inc.







LU3X31T-T64 equivalent, schematic
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description (continued)
100Base-TX Transceiver
LU3X31T-T64 implements a TP-PMD compliant trans-
ceiver for 100Base-TX operation. The differential trans-
mit driver is shared by the 10Base-T and 100Base-TX
subsystems. This arrangement results in one device
that uses the same external magnetics for both the
10Base-T and the 100Base-TX transmission with sim-
ple RC component connections. The individually wave-
shaped 10Base-T and 100Base-TX transmit signals
are multiplexed in the transmit output driver.
Transmit Drivers
The LU3X31T-T64 100Base-TX transmit driver imple-
ments MLT-3 translation and wave-shaping functions.
The rise/fall time of the output signal is closely con-
trolled to conform to the target range specified in the
ANSI TP-PMD standard.
Twisted-Pair Receiver
For 100Base-TX operation, the incoming signal is
detected by the on-chip twisted-pair receiver that com-
prises the differential line receiver, an adaptive equal-
izer, and baseline wander compensation circuits.
The LU3X31T-T64 uses an adaptive equalizer which
changes filter frequency response in accordance with
cable length. The cable length is estimated based on
the incoming signal strength. The equalizer tunes itself
automatically for any cable length to compensate for
amplitude and phase distortions incurred from the
cable.
10Base-T Module
The 10Base-T Transceiver Module is IEEE 802.3 com-
pliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, waveshaper, and link
integrity functions, as defined in the standard. Figure 4
provides an overview for the 10Base-T module.
The LU3X31T-T64 10Base-T module is comprised of
the following functional blocks:
s Manchester encoder and decoder
s Collision detector
s Link test function
s Transmit driver and receiver
s Serial and parallel interface
s Jabber and SQE test functions
s Polarity detection and correction
TPRX±
RECEIVE
FILTER
FILTER
SMART
SQUELCH
CLOCK
RECOVERY
10BASE-T
RECEIVE
PCS
10 Mbit PHY
LOOPBACK
PATH
TPTX±
10/100
TRANSMIT
DRIVER
WAVE
SHAPER
10BASE-T
TRANSMIT
PCS
Figure 4. 10Base-T Module Data Path
RXCLK
CRS
RXDV
RXD[3:0]
COL
TXEN
TXER
TXD[3:0]
TXCLK
5-6782(F)r3
16 Lucent Technologies Inc.










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