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PDF ( 数据手册 , 数据表 ) 10020EV8

零件编号 10020EV8
描述 ECL programmable array logic
制造商 NXP Semiconductors
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10020EV8 数据手册, 描述, 功能
Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
Product specification
10H20EV8/10020EV8
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL® device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
Ultra high speed ECL device
tPD = 4.5ns (max)
tIS = 2.6ns (max)
tCKO = 2.3ns (max)
fMAX = 208MHz
Universal ECL Programmable Array Logic
8 user programmable output macrocells
Up to 20 inputs and 8 outputs
Individual user programmable output
polarity
Variable product term distribution allows
increased design capability
Asynchronous Preset and Reset capability
10KH and 100K options
Power-up Reset and Preload function to
enhance state machine design and testing
Design support provided via SNAP and
other CAD tools
Security fuse for preventing design
duplication
Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
PIN CONFIGURATIONS
F Package
I1 1
I2 2
CLK/I12 3
F1 4
F2 5
VCO1 6
F3 7
F4 8
I3 9
I4 10
I5 11
VEE 12
F = Ceramic DIP (300mil-wide)
24 VCC
23 I11
22 I10
21 F8
20 F7
19 VCO2
18 F6
17 F5
16 I9
15 I8
14 I7
13 I6
A Package
CLK/I12 I2 I1 NC VCC I11 I10
4 3 2 1 28 27 26
F1 5
F2 6
VCO1 7
NC 8
25 F8
24 F7
23 VCO2
22 NC
F3 9
21 F6
F4 10
20 F5
I3 11
19 I9
12 13 14 15 16 17 18
I4 I5 VEE NC I6 I7 I8
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line (300mil-wide)
28-Pin Plastic Leaded Chip Carrier
ORDER CODE
10H20EV8–4F
10020EV8–4F
10H20EV8–4A
10020EV8–4A
DRAWING NUMBER
0586B
0401F
®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
October 22, 1993
113
853–1423 11164







10020EV8 pdf, 数据表
Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
Product specification
10H20EV8/10020EV8
AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier)
10H20EV8: 0°C Tamb +75°C, VEE = –5.2V ± 5%, VCC = VCO1 = VCO2 = GND
10020EV8: 0°C Tamb +85°C, –4.8V VEE –4.2V, VCC = VCO1 = VCO2 = GND
LIMITS1
SYMBOL PARAMETER
FROM
TO
0°C
+25°C
MIN
TYP3
MAX
2
MIN
TYP3
MAX
2
+75°C/+85°C
MIN
TYP3
MAX
2
UNIT
Pulse Width
tCKH
Clock High
tCKL
Clock Low
tCKP
Clock Period
tPRH
Preset/Reset Pulse
Setup and Hold Time
CLK +
CLK –
CLK +
(I, I/O) ±
CLK –
CLK +
CLK +
(I, I/O) ±
2.0
2.0
4.0
4.5
0.6
0.9
2.0 0.6
2.0 0.9
4.0
4.5 —
2.0 0.6
2.0 0.9
4.0
4.5 —
ns
ns
ns
ns
tIS
tIH
tPRS
Input
Input
Clock Resume after
Preset/Reset
(I, I/O) ±
CLK +
(I, I/O) ±
CLK +
(I, I/O) ±
CLK +
2.5
0
4.5
1.0
<0
1.0
2.5 1.1
0 <0
4.5 0.9
2.6 1.4
0 <0
4.5 0.8
ns
ns
ns
Propagation Delay
tPD Input
(I, I/O) ± I/O ±
2.85 4.5
2.95 4.5
3.35 4.5 ns
tCKO
Clock
CLK +
I/O ±
1.65 2.2
1.7 2.2
2.0 2.3 ns
tOE Output Enable
(I, I/O) ±
I/O
2.0 4.0
2.1 4.0
2.2 4.0 ns
tOD Output Disable
(I, I/O) ±
I/O
2.0 4.0
2.1 4.0
2.2 4.0 ns
tPRO
Preset/Reset
(I, I/O) ± I/O ±
2.8 4.5
3.0 4.5
3.5 4.5 ns
tPPR
Power-on Reset
VEE I/O
— 10
— 10
— 10 ns
fMAX
212 377
212 357
204 294
MHz
NOTES:
1. Refer to AC Test Circuit and Voltage Wafeforms diagrams.
2. Maximum loading conditions: 89 fuses intact per row.
3. Typical loading conditions: 15 fuses intact per row. (All “inactive” fuses, except those necessary for correct functionality, are removed.)
October 22, 1993
120







10020EV8 equivalent, schematic
Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
Product specification
10H20EV8/10020EV8
SNAP
Features
Schematic entry using DASH4.0 or
above or OrCADSDT III
State Equation Entry
Boolean Equation Entry
Allows design entry in any combination of
above formats
Simulator
Logic and fault simulation
Timing model generation for device
timing simulation
Synthetic logic analyzer format
Macro library for standard TTL and user
defined functions
Device independent netlist generation
JEDEC fuse map generated from netlist
SNAP (Synthesis, Netlist, Analysis and
Program) is a versatile development tool that
speeds the design and testing of PML. SNAP
combines a user-friendly environment and
powerful modules that make designing with
PML simple. The SNAP environment gives
the user the freedom to design independent
of the device architecture.
The flexibility in the variations of design entry
methodologies allows design entry in the
most appropriate terms. SNAP merges the
inputs, regardless of the type, into a high-
level netlist for simulation or compilation into
a JEDEC fuse map. The JEDEC fuse map
can then be transferred from the host
computer to the device programer.
SNAP’s simulator uses a synthetic logic
analyzer format to display and set the nodes
of the design. The SNAP simulator provides
complete timing information, setup and
hold-time checking, plus toggle and fault
grading analysis.
SNAP operates on an IBM® PC/XT, PC/AT,
PS/2, or any compatible system with DOS
2.1 or higher. A minimum of 640K bytes of
RAM is required together with a hard disk.
DESIGN SECURITY
The 10H20EV8/10020EV8 has a
programmable security fuse that controls the
access to the data programmed in the device.
By using this programmable feature,
proprietary designs implemented in the
device cannot be copied or retrieved.
October 22, 1993
128










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