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PDF ( 数据手册 , 数据表 ) HM1-6504883

零件编号 HM1-6504883
描述 4096 x 1 CMOS RAM
制造商 Intersil Corporation
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HM1-6504883 数据手册, 描述, 功能
HM-6504/883
March 1997
4096 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
PACKAGE TEMPERATURE RANGE
200ns
CERDIP
-55oC to +125oC
HM1-6504B/883
300ns
HM1-6504/883
PKG. NO
F18.3
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
Q7
W8
GND 9
18 VCC
17 A6
16 A7
15 A8
14 A9
13 A10
12 A11
11 D
10 E
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-134
File Number 2993.1







HM1-6504883 pdf, 数据表
HM-6504/883
Timing Waveforms (Continued)
(7)
TAVEL
(8)
TELAX
A ADD VALID
E (6)
TEHEL
W
(18) TELEL
(5) TELEH
(10)
(9) TWLEH
TWLWH
(14)
TDVWL
(16)
TWLDX
D DATA VALID
HIGH Z
Q
(3)
TELQX
(7)
TAVEL
NEXT ADD
(6)
TEHEL
(4)
TEHQZ
HIGH Z
TIME
REFERENCE
TIME
REFERENCE
-1
0
1
2
3
4
5
-1 0
1
2
34
5
FIGURE 3. LATE WRITE CYCLE
TRUTH TABLE
INPUTS
OUTPUTS
EWA D
Q
FUNCTION
HXXX
Z Memory Disabled
HVX
Z Cycle Begins, Addresses are Latched
L
XV
X Write Begins, Data is Latched
LHXX
X Write In Progress Internally
HXX
X Write Completed
HXXX
Z Prepare for Next Cycle (Same as -1)
HVX
Z Cycle Ends, Next Cycle Begins (Same as 0)
The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write, the
output is guaranteed valid at access time. The late write is
between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
6-141














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