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PDF ( 数据手册 , 数据表 ) HUF75545S3

零件编号 HUF75545S3
描述 75A/ 80V/ 0.010 Ohm/ N-Channel/ UltraFET Power MOSFET
制造商 Fairchild Semiconductor
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HUF75545S3 数据手册, 描述, 功能
HUF75545P3, HUF75545S3, HUF75545S3S
Data Sheet
September 2002
75A, 80V, 0.010 Ohm, N-Channel,
UltraFET® Power MOSFET
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
HUF75545P3
HUF75545S3S
JEDEC TO-262AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
HUF75545S3
Symbol
D
G
S
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.010Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75545P3
TO-220AB
75545P
HUF75545S3
TO-262AA
75545S
HUF75545S3S
TO-263AB
75545S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75545S3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HUF75545P3, HUF75545S3,
HUF75545S3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous
Continuous
(TC=
(TC=
2150o0CoC, V, VGGSS==101V0V) )(F(Figiugruere2)2).
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ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
80
80
±20
75
73
Figure 4
Figure 6
V
V
V
A
A
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
270
1.8
-55 to 175
300
260
W
W/oC
oC
oC
oC
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C







HUF75545S3 pdf, 数据表
HUF75545P3, HUF75545S3, HUF75545S3S
SABER Electrical Model
REV 21 may 1999
template huf75545 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.6e-12, cjo = 4.6e-9, tt = 3.3e-8, m = 0.55)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 4.8e-9, is = 1e-30, vj=1.0, m = 0.8 )
m..model mmedmod = (type=_n, vto = 3.04, kp = 6, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.5)
c.ca n12 n8 = 5.4e-9
c.cb n15 n14 = 5.3e-9
DPLCAP
10
RSLC2
5
RSLC1
51
ISCL
RDBREAK
72
LDRAIN
DRAIN
2
RLDRAIN
RDBODY
c.cin n6 n8 = 3.4e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.1e-9
l.lsource n3 n7 = 4.4e-9
GATE
1
LGATE
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
-
ESG
6
8
+
EVTEMP
RGATE + 18 -
9 20 22
6
EVTHRES
+ 19 -
8
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
71
DBODY
LSOURCE
SOURCE
3
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -1e-6
res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6
res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5
res.rdrain n50 n16 = 4.8e-3, tc1 = 9e-3, tc2 = 2.8e-5
res.rgate n9 n20 = 0.87
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51
res.rlsource n3 n7 = 44
res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 2e-5
res.rslc2 n5 n50 = 1e3
S1A
12 13
8
S2A
14 15
13
S1B
S2B
CA 13 CB
+ + 14
EGS
6
8
-
EDS
5
8
-
RBREAK
17 18
RVTEMP
19
IT -
VBAT
+
8
22
res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e-6
RVTHRES
res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7
res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5
spe.ebreak n11 n7 n17 n18 = 87.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3))
}
}
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C














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