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PDF ( 数据手册 , 数据表 ) ADE3050

零件编号 ADE3050
描述 LCD Display Engines with Integrated DVI/ ADC and YUV Ports
制造商 STMicroelectronics
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ADE3050 数据手册, 描述, 功能
ADE3000 ADE3050 ADE3100
ADE3200 ADE3250 ADE3300
®
LCD Display Engines
with Integrated DVI, ADC and YUV Ports
The ADE3xxx is a family of highly integrated display engine ICs, enabling the most advanced, flexible, and
cost-effective system-on-chip solutions for LCD display applications. The ADE3xxx line-up covers the full
range of applications from XGA analog only to dual SXGA Smart Panel designs. All twelve ADE3xxx
devices are pin-to-pin compatible and use a common software platform.
Feature Overview
s Programmable Context Sensitive™ Scaling
s High-quality up-scaling and down-scaling
s Dual Input: DVI / VGA
s Integrated 9-bit ADC/PLL
s Integrated DVI-Rx
s IQSync™ AutoSetup
s Integrated programmable timing controller
s Integrated Pattern generator
s Perfect Picture™ Technology
s sRGB 3D Color Warp
s Integrated OSD
s Advanced EMI reduction features
s Framelock operation with Safety Mode™
s Serial I²C interface
s Low power 0.18 µm process technology
208-pin PQFP Package
Product Selector
Product
ADE3000
ADE3000T
ADE3000SX
ADE3000SXT
ADE3050
ADE3050T
ADE3050SX
ADE3050SXT
ADE3100
ADE3200
ADE3250
ADE3300
Input Interface Support
Analog DVI YUV
xx
xx
xx
xx
xx
xx
xx
xx
x xx
x xx
x xx
x xx
Output Format Support
Resolution
TCON
Up to XGA 75Hz
Up to XGA 75Hz
x
Up to SXGA 75Hz
Up to SXGA 75Hz
x
Up to XGA 75Hz
Up to XGA 75Hz
x
Up to SXGA 75Hz
Up to SXGA 75Hz
x
Up to XGA 75Hz
Up to XGA 75Hz
Up to SXGA 75Hz
x
x
Up to SXGA 75Hz
October 2003
1/88







ADE3050 pdf, 数据表
Pin Description
Pin #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Name
AGND
AVDD18
XGND
XTAL_IN
XTAL_OUT
XVDD18
LVDD18
LGND
CSYNC
VSYNC
HSYNC
AGND
AGND
AVDD33
AVDD33
AGND
AVDD18
AGND
REFB
REFMB
REFPB
AGND
AGND
INB
AVDD33
AVDD33
REFCB
AGND
AVDD18
AVDD18
REFG
REFMG
REFPG
AGND
AGND
ING
AVDD33
AVDD33
REFCG
Table 2: Pin Description (Sheet 3 of 7)
Type
Power
Power
Power
Input
Output
Power
Power
Power
Input
Input
Input
Power
Power
Power
Power
Power
Power
Power
Passive
Passive
Passive
Power
Power
Input
Power
Power
Passive
Power
Power
Power
Passive
Passive
Passive
Power
Power
Input
Power
Power
Passive
Description
Analog Ground
Analog 1.8V VDD
Crystal Oscillator Ground
Crystal Oscillator Input
Crystal Oscillator Output
Crystal Oscillator 1.8V VDD
Line Lock PLL 1.8V VDD
Line Lock PLL Ground
Composite Sync Input - for Sync On Green
Vertical Sync Input
Horizontal (or Composite) Sync Input
Analog Ground
Analog Ground
Analog 3.3V VDD
Analog 3.3V VDD
Analog Ground
Analog 1.8V VDD
Analog Ground
1% 15.0 kOhm resistor to Analog Ground
Connect to Analog Ground
470nF capacitor to Analog Ground
Analog Ground
Analog Ground
Analog Video Port: Blue Channel input
Analog 3.3V VDD
Analog 3.3V VDD
100nF capacitor to Analog Ground
Analog Ground
Analog 1.8V VDD
Analog 1.8V VDD
1% 15.0 kOhm resistor to Analog Ground
Connect to Analog Ground
470nF capacitor to Analog Ground
Analog Ground
Analog Ground
Analog Video Port: Green Channel input
Analog 3.3V VDD
Analog 3.3V VDD
100nF capacitor to Analog Ground
8/88
ADE3XXX







ADE3050 equivalent, schematic
Global Control Block
Register Name
GLBL_SCLK_SYNTH_CTRL
GLBL_SCLK_MD_SD
GLBL_SCLK_PE_L
GLBL_SCLK_PE_H
GLBL_TST_CTRL
GLBL_ADC_CLK_SRC_SEL
GLBL_SCLK_CTRL
GLBL_TCON_BPAD_EN
ADE3XXX
Table 4: Global Registers (Sheet 3 of 4)
Addr.
0x0009
Mode
R/W
R/W
R/W
R/W
0x000A R/W
R/W
0x000B R/W
0x000C
0x000D
R/W
R/W
R/W
0x0010
R/W
R/W
0x0011 R/W
Bits
[7:5]
[4:3]
[2]
[1]
[0]
[7:3]
[2:0]
[7:0]
[7:0]
[7:1]
[0]
[7:3]
[2:0]
[7:5]
[4]
[3]
[2:0]
[7:0]
Default
Description
0x0 Reserved
0x0 XTAL frequency multiplier NDIV
0x0: fXCLK = 54MHz
0x1: fXCLK = 27MHz (normal)
0x2: fXCLK = 13.5MHz
0x3: Reserved
0x0 SCLK frequency synthesizer EXT_PLL
(normal operation = 0)
0x0 SCLK frequency synthesizer PLL_SEL
(normal operation = 1)
0x1 SCLK freq synth control disable (normal
operation = 0)
0x0 SCLK frequency synthesizer MD, range is
[16,31]
0x0 SCLK frequency synthesizer SDIV, range is
[0,7]
0x0 SCLK frequency synthesizer PE, range is [0,
32767]
0x0 Reserved
0x0 Functional Test Mode Enable
Reserved
0x5 ADC Sample Clock Source
0x0: YUVCLK pin
0x1: LLK_PLL (normal)
0x2: SCLK freq synth
0x3: CLKIN pin
0x4: FM freq synth
0x5: Crystal Clock
0x6: 0
0x7: Reserved
0x0 Reserved
0x0 Invert SCLK
Reserved
0x0 SCLK source select
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: FM freq synth (normal)
0x3: inclk source
0x4: CLKIN pin
0x5: crystal clock
0x6: 0
0x7: Reserved
0x0 For each bit n (0 to 7),
0: TCON[n] pin is TCON output
1: TCON[n] pin is input into TVI block
16/88










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