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PDF ( 数据手册 , 数据表 ) ADC0808CCN

零件编号 ADC0808CCN
描述 P Compatible 8-Bit A/D Converter with 8-Channel Multiplexer
制造商 Micro Linear Corporation
LOGO Micro Linear Corporation LOGO 


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ADC0808CCN 数据手册, 描述, 功能
May 1997
ML2258*
µP Compatible 8-Bit A/D Converter
with 8-Channel Multiplexer
GENERAL DESCRIPTION
The ML2258 combines an 8-bit A/D converter, 8-channel
analog multiplexer, and a microprocessor compatible 8-
bit parallel interface and control logic in a single
monolithic device.
Easy interface to microprocessors is provided by the
latched and decoded multiplexer address inputs and
latched three-state outputs.
The device is suitable for a wide range of applications
from process and machine control to consumer,
automotive, and telecommunication applications.
The ML2258 is an enhanced, pin-compatible, second
source for the industry standard ADC0808/ADC0809. The
ML2258 enhancements are faster conversion time, true
sample and hold function, superior power supply
rejection, wider reference range, and a double buffered
data bus as well as faster digital timing. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.
BLOCK DIAGRAM
FEATURES
s Conversion time
6.6µs
s Total unadjusted error
±1/2LSB or ±1LSB
s No missing codes
s Sample and hold
390ns acquisition
s Capable of digitizing a 5V, 50kHz sine wave
s 8-input multiplexer
s 0V to 5V analog input range with single 5V
power supply
s Operates ratiometrically or with up to 5V
voltage reference
s No zero-or full-scale adjust required
s Analog input protection
25mA per input min
s Low power dissipation
3mA max
s TTL and CMOS compatible digital inputs and outputs
s Standard 28-pin DIP or surface mount PCC
s Superior pin compatible replacement for ADC0808 and
ADC0809
* Some Packages Are End Of Life As Of August 1, 2000
START CLOCK
IN0
IN1
IN2
IN3 8-CHANNEL
MULTIPLEXER
IN4
IN5
IN6
IN7
ADDR0
ADDR1
ADDR2
ADDRESS
LATCH ENABLE
ADDRESS
LATCH
AND
DECODER
A/D WITH
SAMPLE HOLD
CONTROL & TIMING
END OF CONVERSION
(INTERRUPT)
COMPARATOR
S.A.R.
SWITCH TREE
THREE
STATE
OUTPUT
LATCH
BUFFER
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCC GND +VREF
CAPACITOR/
RESISTOR
ARRAY
–VREF OUTPUT
ENABLE
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ADC0808CCN pdf, 数据表
ML2258
valid on DB0–DB7 until the next conversion updates the
data word on the next rising edge of EOC.
A conversion can be interrupted and restarted at any time by
a new START pulse.
1.3 ANALOG INPUTS AND SAMPLE/HOLD
The ML2258 has a true sample and hold circuit which
samples both the selected input and ground
simultaneously. This simultaneous sampling with a true
S/H will give common mode rejection and AC linearity
performance that is superior to devices where the two
input terminals are not sampled at the same instant and
where true sample and hold capability does not exist.
Thus, the ML2258 can reject AC common mode signals
from DC–50kHz as well as maintain linearity for signals
from DC–50kHz.
The plot below (figure 6) shows a 2048 point FFT of the
ML2258 converting a 50kHz, 0 to 5V, low distortion sine
wave input. The ML2258 samples and digitizes, at its
specified accuracy, dynamic input signals with frequency
components up to the Nyquist frequency (one-half the
sampling rate). The output spectra yields precise
measurements of input signal level, harmonic components,
and signal to noise ratio up to the 8-bit level. The near-ideal
signal to noise ratio is maintained independent of increasing
analog input frequencies to 50kHz.
The signal at the analog input is sampled during the
interval when the sampling switch is open prior to
conversion start. The sampling window (S/H acquisition
time) is 4 CLK periods long and occurs 4 CLK periods after
START goes low. When the sampling switch closes at the
start of the S/H acquisition time, 8pF of capacitance is
thrown onto the analog input. 4 CLK periods later, the
sampling switch opens, the signal present at analog input
is stored and conversion starts. Since any error on the
analog input at the end of the S/H acquisition time will
cause additional conversion error, care should be taken to
insure adequate settling and charging time from the
source. If more charging or settling time is needed to
reduce these analog input errors, a longer CLK period can
be used.
The ML2258 has improved latchup immunity. Each analog
input has dual diodes to the supply rails, and a minimum
of ±25mA (±100mA typically) can be injected into each
analog input without causing latchup.
1.4 REFERENCE
The voltage applied to the +VREF and –VREF inputs defines
the voltage span of the analog input (the difference
between VINMAX and VINMIN) over which the 256 possible
output codes apply. The devices can be used in either
ratiometric applications or in systems requiring absolute
accuracy. The reference pins must be connected to a
voltage source capable of driving the reference input
resistance, typically 20.
In a ratiometric system, the analog input voltage is
proportional to the voltage used for the A/D reference.
This voltage is typically the system power supply, so the
+VREF pin can be tied to VCC and –VREF tied to GND. This
technique relaxes the stability requirements of the system
reference as the analog input and A/D reference move
together maintaining the same output code for a given
input condition.
For absolute accuracy, where the analog input varies
between specific voltage limits, the reference pins can be
biased with a time and temperature stable voltage source.
In contrast to the ADC0808 and ADC0809, the ML2258
–VREF and +VREF reference values do not have to be
symmetric around one half of the supply. +VREF and
–VREF can be at any voltage between VCC and GND. In
addition, the difference between +VREF and –VREF can be
set to small values for conversions over smaller voltage
ranges. Particular care must be taken with regard to noise
pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
37.5
FREQUENCY (kHz)
75
Figure 6. Output Spectrum
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